Multi-port memory using single-port memory cells
First Claim
1. A memory operative to provide multi-port access functionality, the memory comprising:
- a plurality of single-port memory cells forming a first memory array, the first memory array being organized into a plurality of memory banks, each of the memory banks comprising a corresponding subset of the plurality of single-port memory cells;
a second memory array, the second memory array comprising a plurality of multi-port memory cells and being operative to store status information of data stored in corresponding locations in the first memory array;
at least one cache memory operatively connected with the first memory array, the cache memory being operative to store data for resolving concurrent read and write access conflicts to the first memory array during a same memory cycle; and
a controller operative;
to receive the status information from the second memory array and to determine a validity of data stored in the first memory array as a function of the status information;
to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory as a function of the status information; and
to resolve concurrent read and write access conflicts to the first memory array during the same memory cycle.
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Accused Products
Abstract
A memory operative to provide multi-port functionality includes multiple single-port memory cells forming a first memory array. The first memory array is organized into multiple memory banks, each of the memory banks comprising a corresponding subset of the single-port memory cells. The memory further includes a second memory array including multiple multi-port memory cells and is operative to track status information of data stored in corresponding locations in the first memory array. At least one cache memory is connected with the first memory array and is operative to store data for resolving concurrent read and write access conflicts in the first memory array. The memory includes a controller operative: to receive the status information and to determine a validity of data stored in the first memory array as a function of the status information; to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory; and to resolve concurrent read and write access conflicts in the first memory array during the same memory cycle.
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Citations
23 Claims
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1. A memory operative to provide multi-port access functionality, the memory comprising:
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a plurality of single-port memory cells forming a first memory array, the first memory array being organized into a plurality of memory banks, each of the memory banks comprising a corresponding subset of the plurality of single-port memory cells; a second memory array, the second memory array comprising a plurality of multi-port memory cells and being operative to store status information of data stored in corresponding locations in the first memory array; at least one cache memory operatively connected with the first memory array, the cache memory being operative to store data for resolving concurrent read and write access conflicts to the first memory array during a same memory cycle; and a controller operative;
to receive the status information from the second memory array and to determine a validity of data stored in the first memory array as a function of the status information;
to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory as a function of the status information; and
to resolve concurrent read and write access conflicts to the first memory array during the same memory cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An integrated circuit, comprising:
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at least one memory operative to provide multi-port access functionality, the at least one memory comprising; a plurality of single-port memory cells forming a first memory array, the first memory array being organized into a plurality of memory banks, each of the memory banks comprising a corresponding subset of the plurality of single-port memory cells; a second memory array, the second memory array comprising a plurality of multi-port memory cells and being operative to store status information of data stored in corresponding locations in the first memory array; at least one cache memory operatively connected with the first memory array, the cache memory being operative to store data for resolving concurrent read and write access conflicts to the first memory array during a same memory cycle; and a controller operative;
to receive the status information from the second memory array and to determine a validity of data stored in the first memory array as a function of the status information;
to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory as a function of the status information; and
to resolve concurrent read and write access conflicts to the first memory array during the same memory cycle.
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22. A memory operative to provide n-port access functionality, where n is an integer greater than one, the memory comprising:
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a plurality of m-port memory cells forming a first memory array, the first memory array being organized into a plurality of memory banks, each of the memory banks comprising a corresponding subset of the plurality of m-port memory cells, where m is an integer less than n; a second memory array, the second memory array comprising a plurality of multi-port memory cells and being operative to track status information of data stored in corresponding locations in the first memory array; at least one cache memory operatively connected with the first memory array, the cache memory being operative to store data for resolving concurrent read and write access conflicts to the first memory array during a same memory cycle; and a controller operative;
to receive the status information from the second memory array and to determine a validity of data stored in the first memory array as a function of the status information;
to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory as a function of the status information; and
to resolve concurrent read and write access conflicts to the first memory array during the same memory cycle.
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23. An electronic system, comprising:
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at least one integrated circuit, the at least one integrated circuit including at least one memory operative to provide n-port access functionality, where n is an integer greater than one, the at least one memory comprising; a plurality of m-port memory cells forming a first memory array, the first memory array being organized into a plurality of memory banks, each of the memory banks comprising a corresponding subset of the plurality of m-port memory cells, where m is an integer less than n; a second memory array, the second memory array comprising a plurality of multi-port memory cells and being operative to track status information of data stored in corresponding locations in the first memory array; at least one cache memory operatively connected with the first memory array, the cache memory being operative to store data for resolving concurrent read and write access conflicts to the first memory array during a same memory cycle; and a controller operative;
to receive the status information from the second memory array and to determine a validity of data stored in the first memory array as a function of the status information;
to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory as a function of the status information; and
to resolve concurrent read and write access conflicts to the first memory array during the same memory cycle.
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Specification