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Multi-port memory using single-port memory cells

  • US 8,374,050 B2
  • Filed: 06/04/2011
  • Issued: 02/12/2013
  • Est. Priority Date: 06/04/2010
  • Status: Expired due to Fees
First Claim
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1. A memory operative to provide multi-port access functionality, the memory comprising:

  • a plurality of single-port memory cells forming a first memory array, the first memory array being organized into a plurality of memory banks, each of the memory banks comprising a corresponding subset of the plurality of single-port memory cells;

    a second memory array, the second memory array comprising a plurality of multi-port memory cells and being operative to store status information of data stored in corresponding locations in the first memory array;

    at least one cache memory operatively connected with the first memory array, the cache memory being operative to store data for resolving concurrent read and write access conflicts to the first memory array during a same memory cycle; and

    a controller operative;

    to receive the status information from the second memory array and to determine a validity of data stored in the first memory array as a function of the status information;

    to control a manner in which data is stored in the memory for avoiding data overflow in the cache memory as a function of the status information; and

    to resolve concurrent read and write access conflicts to the first memory array during the same memory cycle.

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