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Serial cancellation receiver design for a coded signal processing engine

  • US 8,374,299 B2
  • Filed: 03/30/2011
  • Issued: 02/12/2013
  • Est. Priority Date: 09/28/2001
  • Status: Expired due to Term
First Claim
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1. An apparatus configured for generating an interference suppressed signal, comprising:

  • one or more power estimators configured for computing power estimates of components of a received signal;

    a control block coupled to the one or more power estimators configured to determine an order of suppression of the components of a received signal based at least in part on the power estimates; and

    one or more processing fingers coupled to the control block configured for generating at least one interference suppressed signal stream;

    wherein the one or more processing fingers comprises at least one Hadamard transform module configured to compute the amplitudes of a plurality of channels.

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