Ring bus structure and its use in flash memory systems

• US 8,375,146 B2
• Filed: 08/09/2004
• Issued: 02/12/2013
• Est. Priority Date: 08/09/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sinclair, Alan Welsh
• Primary Examiner(s): Salad, Abdullahi
• Assistant Examiner(s): Keehn, Richard G
• Application Number:
  US10/915,039
• Publication Number:
  US 20060031593A1
• Time in Patent Office: 3,109 Days
• Field of Search: 709/251
• US Class Current: 709/251
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation

Abstract

A system and integrated circuit chips used in the system utilize a bus in the form of a ring to interconnect nodes of individual components for transfer of data and commands therebetween. An example system described is a memory having one or more re-programmable non-volatile memory cell arrays connected to each other and to a system controller by a ring bus.

Claims

1. A method of operating a memory system, said system comprising a plurality of re-programmable non-volatile memory units that each includes a data communications node and that each comprises memory storage cells grouped into blocks of memory cells that are simultaneously erased prior to reprogramming, by transferring data around a ring bus connecting said nodes and a controller together, said method comprising:

passing controller configuration commands that include node identification information in a given direction around the ring bus from the controller to the command and data communications nodes, said node identification information in each of the configuration commands including information for identifying nodes to be established as source or destination nodes, the configuration commands being acted upon only by the nodes identified by said node identification information, causing nodes of a plurality of the memory units identified in a controller configuration command to be established as source nodes from which data is to be transferred through a subsequent controller transfer command and causing the nodes of a plurality of the memory units identified in the controller configuration command to be established as destination nodes to which data is to be transferred through a subsequent controller transfer command, wherein no data transfer occurs when said controller commands are passed around the ring bus,

reading data to be transferred from the plurality of memory units of source nodes into temporary data storage provided at said source nodes,

thereafter issuing said subsequent controller transfer command to transfer the read data from the temporary data storage at said source nodes to the data lines substantially simultaneously only in the given direction around the ring bus,

writing the transferred read data in the data lines into temporary data storage provided at said destination nodes, and

thereafter writing the transferred data from the temporary data storage at said destination nodes into the plurality of memory units of said destination nodes,

wherein transferring the read data includes transferring data around the ring bus from said of source nodes in at least two sequential time slots and said at least two sequential time slots defining a cycle of C sequential time slots, and N time slots being used in the transferrin of read data, N and C being positive integers, wherein transferrin the read data additionally includes inserting one or more unused time slots so that N is equal to the total number of nodes on the ring bus minus the number of unused time slots, and adjusting N and C to reduce a number of any unused time slots.

2. The method of claim 1, wherein passing said controller configuration command around the ring bus includes passing said controller configuration command from the controller through a controller node connected into the ring bus.

3. The method of claim 2, which additionally comprises transferring data to and from a host through buffer memory included within the controller and the controller node.

4. The method of claim 1, which additionally comprises transferring data to and from a host through another node connected into the ring bus.

5. The method of claim 1,

wherein writing the transferred data includes writing the data being transferred into said plurality of destination nodes from different ones of said at least two sequential time slots, and said subsequent controller transfer command causes a simultaneous transfer of multiple channels of data from said plurality of source nodes to said plurality of destination nodes in a single direction over a number of time-multiplexed data frames.

6. The method of claim 5, wherein passing controller commands around the ring bus does not include the use of sequential time slots.

7. The method of claim 1, wherein transferring the read data around the ring bus includes transferring the read data completely around the ring from said at least one source node and back to said at least one source node.

8. The method of claim 7, which additionally comprises verifying at said at least one source node the validity of the read data after being transferred completely around the ring, wherein verifying the validity of the read data includes comparing the read data after being transferred completely around the ring with the read data placed on the ring bus at said at least one source node.

9. The method of claim 8, which additionally comprises checking all of the read data around the ring bus with an error correction scheme at a location on the ring bus.

10. The method of claim 9, wherein checking the read data with an error correction scheme occurs in the controller.

11. The method of claim 10, wherein checking the read data with an error correction scheme includes passing all of the read data around the ring bus through error correction circuitry connected to the ring bus through a node in addition to said at least one source node and said at least one destination node.

12. The method of claim 1, wherein the controller configuration command passed around the ring bus to establish at least one of the nodes as a source of data to be transferred and at least one other of the nodes as a destination of data to be transferred originate only with the controller.

13. The method of claim 1, which additionally comprises, prior to transferring the read data around the ring bus, sending controller commands and data around the ring bus from the controller to configure the plurality of nodes.

14. The method of claim 1, wherein transferring the read data around the ring bus includes imposing a delay at individual ones of the plurality of nodes of one or more cycles of a system clock source to which the transferring read data are synchronized.

15. The method of claim 1, wherein passing said controller configuration command around the ring bus includes doing so on at least a first conductor of the ring bus and transferring the read data around the ring bus includes doing so on at least a second conductor of the ring bus different from the first conductor.

16. The method of claim 1, wherein passing said controller configuration command around the ring bus includes (1) establishing said at least one of the nodes as a source of data by at least one other of the plurality of nodes receiving the controller configuration commands and then configuring said at least one of the nodes as a source of data, and (2) establishing said at least one of the nodes as a destination of data by at least one other of the plurality of nodes receiving the controller configuration commands and then configuring said at least one of the nodes as a destination of data.

17. The method of claim 1, wherein writing the transferred data into the memory connected with said at least one destination node includes writing the transferred data into at least a second unit of re-programmable non-volatile memory cells that are connected to said at least one destination node.

18. The method of claim 17, wherein the first and second units of memory cells include respective first and second planes of less than all the memory cells on a single integrated circuit chip.

19. The method of claim 17, wherein the first and second units of memory cells include an entire memory cell array on respective first and second integrated circuit chips.

20. The method of claim 2, which additionally comprises temporarily storing the read data in a buffer memory connected to another of the plurality of nodes different from the controller node, said at least one source node and said at least one destination node.

21. The method of claim 1, wherein reading data into temporary data storage includes transferring the read data into one of at least two data registers provided at said at least one source node.

22. The method of claim 1, wherein writing data into temporary data storage includes writing the transferred data into one of at least two data registers provided at said at least one destination node.

23. The method of claim 1, which additionally comprises simultaneously reading a second set of data from memory connected to one of the plurality of nodes into one portion of temporary data storage at said one of the plurality of nodes and writing a third set of data from the ring bus into another portion of temporary data storage at said one of the plurality of nodes.

24. A memory system, comprising:

a plurality of re-programmable non-volatile memory units that each includes a data communications node, and that each comprises memory storage cells grouped into blocks of memory cells that are simultaneously erased prior to reprogramming,

a host data input/output circuit having another data communications node,

a bus connecting the individual data communication nodes together in a ring, and

a controller including a micro-controller operably connected with the ring bus to cause a simultaneous transfer of multiple channels of data from a plurality of the data communications nodes completely around the ring bus in a single direction over a number of time-multiplexed data frames adapted to include the number of multiple channels of data being transferred, said controller passing controller configuration commands that include node identification information in a given direction around the ring bus from the controller to the nodes, said node identification information in each of the configuration commands including information for identifying nodes to be established as source or destination nodes, the configuration commands being acted upon only by nodes addressed by such node identification information, in order to establish nodes of a plurality of the memory units identified in the controller configuration command as source nodes from which data is to be transferred through a subsequent controller transfer command and to establish the nodes of a plurality of the memory units identified in the controller configuration command as destination nodes to which data is to be transferred through a subsequent controller transfer command, wherein no data transfer occurs when said controller configuration commands are passed around the ring bus, said controller thereafter issuing said subsequent controller transfer command to transfer data from the source nodes to the destination nodes in the given direction around the ring bus,

wherein transferring the read data includes transferring data around the ring bus from said plurality of source nodes in at least two sequential time slots and said at least two sequential time slots defining a cycle of C sequential time slots, and N time slots being used in the transferring of read data, N and C being positive integers, wherein transferring the read data additionally includes inserting one or more unused time slots so that N is equal to the total number of nodes on the ring bus minus the number of unused time slots, and adjusting N and C to reduce a number of any unused time slots.

25. The memory system of claim 24, wherein the controller is further operably connected through the ring bus to send controller configuration commands over the ring bus to selected ones of the communication nodes for transfer of data therethrough.

26. The memory system of claim 25, wherein the at least one memory unit additionally includes a configuration circuit and a command node connected to the ring bus and the configuration circuit for receiving and executing the controller configuration commands from the controller.

27. The memory system of claim 24, wherein at least the data communications node of the at least one memory unit includes at least two registers connected to simultaneously store at least two pieces of data being transferred between the memory sub-system and the ring bus.

28. The memory system of claim 24, wherein the controller includes the host data input/output circuit and the controller is connected to the ring bus through said another data communications node.

29. The memory system of claim 24, wherein the controller is connected to the ring bus through a command signal node.

30. The memory system of claim 24, wherein the plurality of memory units include two or more memory planes on a single integrated circuit chip.

31. The memory system of claim 24, wherein the plurality of memory units are formed on respective separate integrated circuit chips.

32. The memory system of claim 24, which additionally comprises an error correction circuit operably connected with the ring bus to enable the multiple channels of data to pass therethrough and checked for errors as they are transferred around the ring bus.

33. The memory system of claim 32, wherein the controller includes the error correction circuit.

34. A method of operating a memory system, said system comprising a plurality of re-programmable non-volatile memory units that each includes a data communications node and that each comprises memory storage cells grouped into blocks of memory cells that are simultaneously erased prior to reprogramming, by transferring data around a ring bus connecting said nodes, at least one command node and a controller together, said method comprising:

passing controller configuration commands that include node identification information in a given direction around the ring bus from the controller to the command and data communications nodes, said node identification information in each of the configuration commands including information for identifying the nodes to be established as source or destination nodes, the configuration commands being acted upon only by the nodes identified by said node identification information, causing nodes of a plurality of the memory units identified in a controller configuration command to be established as source nodes from which data is to be transferred through a subsequent controller transfer command and causing the nodes of a plurality of the memory units identified in the controller configuration command to be established as destination nodes to which data is to be transferred through a subsequent controller transfer command, wherein no data transfer occurs when said controller commands are passed around the ring bus,

reading data to be transferred from the plurality of memory units of source nodes into temporary data storage provided at said source nodes, wherein read commands for reading data and the node identification information identifying the source nodes are first stored at the at least one command node and then executed to cause such, transfer of data into the temporary data storage,

thereafter issuing said subsequent controller transfer command to transfer the read data from the temporary data storage at said source nodes to the data lines substantially simultaneously only in the given direction around the ring bus, writing the transferred read data in the data lines into temporary data storage provided at said destination nodes, and

thereafter writing the transferred data from the temporary data storage at said destination nodes into the plurality of memory units of said destination nodes,

wherein transferring the read data includes transferring data around the ring bus from said plurality of source nodes in at least two sequential time slots, and said at least two sequential time slots defining a cycle of C sequential time slots, and N time slots being used in the transferring of read data, N and C being positive integers, wherein transferring the read data additionally includes inserting one or more unused time slots so that N is equal to the total number of nodes on the ring bus minus the number of unused time slots, and adjusting N and C to reduce a number of any unused time slots.

35. The method of claim 34, wherein the ring bus connects said nodes, a plurality of command nodes and a controller together, each of the command nodes associated with corresponding set of one or more memory planes, wherein the node identification information identifying the source nodes of each set of one or more memory planes is stored at the corresponding command node.

36. A memory system, comprising:

a plurality of re-programmable non-volatile memory units that each includes a data communications node, and that each comprises memory storage cells grouped into blocks of memory cells that are simultaneously erased prior to reprogramming,

a host data input/output circuit having another data communications node,

at least one command node,

a bus connecting the individual data communication nodes and said at least one command node together in a ring, and

a controller including a micro-controller operably connected with the ring bus to cause a simultaneous transfer of multiple channels of data from a plurality of the data communications nodes completely around the ring bus in a single direction over a number of time-multiplexed data frames adapted to include the number of multiple channels of data being transferred, said controller passing controller configuration commands that include node identification information in a given direction around the ring bus from the controller to the nodes, said node identification information in each of the configuration commands including information for identifying the nodes to be established as source or destination nodes, the configuration commands being acted upon only by the nodes addressed by such node identification information, in order to establish the nodes of a plurality of the memory units identified in the controller command as source nodes from which data is to be transferred through a subsequent controller transfer command and to establish the nodes of a plurality of the memory units identified in the controller command as destination nodes to which data is to be transferred through a subsequent controller transfer command, wherein no data transfer occurs when said controller configuration commands are passed around the ring bus, said controller thereafter issuing said subsequent controller transfer command to transfer data from the source nodes to the destination nodes in the given direction around the ring bus,

wherein read commands for reading data and the node identification information identifying the source nodes are first stored at the at least one command node and then executed to cause such transfer of data into the temporary data storage,

wherein transferring the read data includes transferring data around the ring bus from said plurality of source nodes in at least two sequential time slots, and said at least two sequential time slots defining a cycle of C sequential time slots, and N time slots being used in the transferring of read data, N and C being positive integers, wherein transferring the read data additionally includes inserting one or more unused time slots so that N is equal to the total number of nodes on the ring bus minus the number of unused time slots, and adjusting N and C to reduce a number of any unused time slots.

37. The system of claim 36, said system comprising a plurality of command nodes, wherein the ring bus connects said nodes, a plurality of command nodes and a controller together, each of the command nodes associated with corresponding set of one or more memory planes, wherein the node identification information identifying the source nodes of each set of one or more memory planes is stored at the corresponding command node.