Memory system and data transmission method

• US 8,375,240 B2
• Filed: 11/13/2008
• Issued: 02/12/2013
• Est. Priority Date: 08/23/2002
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Matsui, Yoshinori
• Primary Examiner(s): Myers, Paul R
• Assistant Examiner(s): Cerullo, Jeremy S
• Application Number:
  US12/270,546
• Publication Number:
  US 20090122587A1
• Time in Patent Office: 1,552 Days
• Field of Search: 713/500
• US Class Current: 713/500
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 13/4256 using a clocked protocol
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.

Claims

1. A memory system comprising:

a memory controller outputting a first signal and a second signal;

a plurality of memory circuits receiving said first and second signals;

a first wiring coupled between said memory controller and each of said plurality of memory circuits commonly to transfer said first signal to said each of said plurality of memory circuits in common;

a plurality of second wirings provided corresponding with said plurality of memory circuits, each of said plurality of second wirings being coupled between said memory controller and an associated one of said plurality of memory circuits independently to transfer said second signal to an associated one of said plurality of memory circuits;

a detection circuit which detects a skew between said first signal and said second signal; and

an adjustment circuit which adjusts a relationship between said first signal and said second signal based on said skew.

2. The memory system according to claim 1, wherein said first signal is a clock signal or a command/address signal, said second signal is a data signal or a timing signal being synchronized with said data signal.

3. The memory system according to claim 1, wherein said first signal is a clock signal, said second signal is a data signal.

4. The memory system according to claim 1, wherein said first signal is a command/address signal, said second signal is a timing signal being synchronized with a data signal.

5. The memory system according to claim 1, further comprising an output circuit which outputs a third signal from each of said plurality of memory circuits to said memory controller, said third signal being based on said first signal or said second signal.

6. The memory system according to claim 5, wherein a third wiring for transmitting said third signal is connected directly between said memory controller and each of said plurality of memory circuits.

7. The memory system according to claim 5, wherein said adjustment circuit adjusts said relationship based on said skew by utilizing said third signal.

8. The memory system according to claim 1, wherein said plurality of memory circuits includes a first and a second memory circuits, a length of said first wiring connected between said first memory circuit and said memory controller is different from a length of said first wiring connected between said second memory circuit and said memory controller, a length of said second wiring connected between said first memory circuit and said memory controller is substantially identical with a length of said second wiring connected between said second memory circuit and said memory controller.

9. The memory system according to claim 8, wherein a size of said skew in said first memory circuit is different from a size of said skew in said second memory circuit.

10. The memory system according to claim 1, wherein a selected one of the plurality of memory circuits, based on the first and second signals, outputs a third signal and a fourth signal to the memory controller, the detection circuit detects a skew between said third and fourth signal, and the adjustment circuit adjusts a relationship between said third signal and said fourth signal based on said skew.

11. A memory module comprising:

a substrate;

a plurality of memory circuits mounted on said substrate, said plurality of memory circuits receiving a first signal and a second signal;

a first wiring configured to commonly couple each of said plurality of memory circuits for transferring said first signal to said each of said plurality of memory circuits in common;

a plurality of second wirings provided corresponding with said plurality of memory circuits, each of said plurality of second wirings configured to couple between a memory controller and an associated one of said plurality of memory circuits independently for transferring said second signal to an associated one of said plurality of memory circuits; and

a detection circuit which detects a skew between said first signal and said second signal.

12. The memory module according to claim 11, further comprising a first wiring transmitting said first signal connected commonly to all of said plurality of memory circuits, a second wiring for transmitting said second signal connected directly to each of said plurality of memory circuits.

13. The memory module according to claim 11, wherein said first signal is a clock signal or a command/address signal, said second signal is a data signal or a timing signal being synchronized with said data signal.

14. The memory module according to claim 11, further comprising an output circuit supplying a third signal based on said first signal or said second signal.

15. The memory module according to claim 11, wherein a selected one of the plurality of memory circuit, based on the first and second signals, outputs a third signal and a fourth signal, the detection circuit detects a skew between said third and fourth signal, and an adjustment circuit adjusts a relationship between said third signal and said fourth signal based on said skew.