System and method for testing a module

• US 8,375,250 B2
• Filed: 03/04/2009
• Issued: 02/12/2013
• Est. Priority Date: 03/04/2009
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mayer, Albrecht, Carl, Wolfram
• Primary Examiner(s): Baderman, Scott
• Assistant Examiner(s): Arcos, Jeison C
• Application Number:
  US12/398,012
• Publication Number:
  US 20100229038A1
• Time in Patent Office: 1,441 Days
• Field of Search: 714/10, 714/19, 712/229, 701/1, 713/300, 710/14, 710/16, 710/200
• US Class Current: 714/25
• CPC Class Codes: H04L 12/40189 by using a plurality of bus systems
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

In an embodiment, a system has a bus interface port, a selection circuit coupled to the bus interface port, a first bus interface circuit coupled to the selection circuit and a second bus interface circuit coupled to the selection circuit. The selection circuit is configured to select between the first bus interface circuit and the second bus interface circuit. The system also has an initialization circuit configured to detect a first codeword written to the bus interface port, and activate the second bus interface circuit if the first codeword is detected.

Claims

1. A method of testing a module comprising a bus interface, the method comprising:

setting a module operating mode to a first mode, setting comprising configuring the bus interface to operate using a first bus interface protocol;

wherein the first interface bus protocol comprises a maximum edge transition rate;

after setting the module to the first operating mode, changing the operating mode from the first operating mode to a second operating mode, changing the operating mode from the first operating mode to the second operating mode comprising

writing a first codeword to the bus interface, the first codeword different from a codeword used within the first bus interface protocol, wherein writing the first codeword to the bus interface comprises operating the bus interface at an edge transition rate exceeding the maximum edge transition rate of the first bus protocol, and

configuring the bus interface to operate using a second bus interface protocol; and

after changing the operating mode to the second operating mode, using the second bus interface protocol for performing tool access of software debug and hardware test infrastructure using the second bus protocol, the software debug and hardware test infrastructure being accessible during the second operating mode.

2. The method of claim 1, wherein the first codeword is not defined in the first bus interface protocol.

3. The method of claim 1, wherein setting the module operating mode further comprises booting the module in the first operating mode.

4. The method of claim 1, wherein:

the first bus interface protocol comprises a Controller Area Network (CAN) interface protocol;

the second bus interface protocol comprises a Debug Access Port (DAP) protocol; and

the first codeword comprises 1024 “

0”

values in a Single Pin DAP (SPD) format.

5. The method of claim 1, wherein:

the first operating mode comprises a normal operating mode; and

the second operating mode comprises a tool access operating mode.

6. The method of claim 1, wherein the maximum edge transition rate is an edge transition every 1 μ

s.

7. The method of claim 1, wherein the first bus interface protocol comprises a Controller Area Network (CAN) interface protocol.

8. The method of claim 7, wherein the second bus interface protocol comprises a Controller Area Network (CAN) interface protocol.

9. The method of claim 7, wherein the second bus interface protocol comprises a Debug Access Port (DAP) protocol.

10. The method of claim 1, further comprising after changing the operating mode from the first operating mode to the second operating mode, activating an application test mode, activating the application test mode comprising issuing an application test mode command on the bus interface, wherein the application test mode command is configured to reboot the module in the application test mode, rebooting comprising initializing registers within the module.

11. The method of claim 10, further comprising:

after activating the application test mode, operating the module in the application test mode, wherein operating the module in the application test mode comprising accessing a JTAG interface within the module.

12. A system comprising:

a bus interface port;

a selection circuit coupled to the bus interface port;

a first bus interface circuit coupled to the selection circuit, the first bus interface circuit configured to operate according to a first bus protocol;

a second bus interface circuit coupled to the selection circuit, wherein the selection circuit is configured to select between the first bus interface circuit and the second bus interface circuit;

an initialization circuit configured to

detect a first codeword written to the bus interface port, wherein the first codeword comprises edge transitions at an edge transition rate exceeding a maximum edge transition rate of the first bus protocol, and

activate the second bus interface circuit if the first codeword is detected;

a controller circuit; and

a test circuit coupled to the controller circuit and to the second bus interface circuit, the test circuit controllable through the bus interface port via the second bus interface circuit.

13. The system of claim 12, further comprising an application test mode initialization circuit coupled to the second bus interface circuit, the application test mode initialization circuit configured to reboot the controller circuit and place the test circuit under the control of the second bus interface circuit after the controller circuit is rebooted.

14. The system of claim 12, further comprising a transceiver coupled to the bus interface Port.

15. The system of claim 12, wherein:

the first bus interface circuit comprises a Controller Area Network (CAN) interface circuit;

the first bus protocol comprises a CAN protocol; and

the second bus interface circuit comprises a Debug Access Port (DAP) interface circuit.

16. An integrated circuit comprising the system of claim 12.

17. An automotive controller comprising the system of claim 12, wherein the bus interface port comprises an exclusive interface to access the test circuit.

18. The system of claim 15, wherein the DAP interface circuit is coupled to the test circuit.

19. The system of claim 15, wherein the first codeword is undefined within the CAN protocol.

20. An automotive controller module comprising:

a printed circuit board (PCB);

a target circuit disposed on the PCB;

a test circuit coupled to the target circuit, the test circuit configured to test the target circuit;

a first interface circuit coupled to the target circuit, the first interface circuit configured to communicate with the target circuit in a normal mode according to a first protocol;

a second interface circuit coupled to the test circuit, the second interface circuit configured to communicate with the test circuit according to a second protocol;

an interface selection circuit, the interface selection circuit configured to select between the first interface circuit and the second interface circuit;

a bus port coupled to the interface selection circuit, wherein the test circuit is controllable through the bus port via the second interface circuit; and

a test mode initialization circuit configured to

detect a first codeword on the bus port, the first codeword different from a codeword defined by the first protocol,

activate the second interface circuit upon detection of the first codeword on the bus port, and

reboot the target circuit and the test circuit into a test mode upon receipt of a second codeword after the second interface has been activated, wherein the first codeword comprises edge transitions at an edge transition rate exceeding a maximum edge transition rate of the first protocol.

21. The automotive controller of claim 20, wherein:

the first interface comprises a Controller Area Network (CAN) interface; and

the target circuit comprises a microcontroller.

22. The automotive controller of claim 20, wherein the test circuit is configured to interface to a JTAG interface.