Methods of manufacturing semiconductor devices and transistors

• US 8,377,779 B1
• Filed: 01/03/2012
• Issued: 02/19/2013
• Est. Priority Date: 01/03/2012
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Yu-Ping
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US13/342,772
• Time in Patent Office: 413 Days
• Field of Search: 438/283, 438/284, 438/197, 438/167, 438/269, 438/481, 257/E21.421, 257/E21.562
• US Class Current: 438/283
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/02225 characterised by the process for the formation of the insulating layer
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods of manufacturing semiconductor devices and transistors are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece comprising a plurality of fins, and forming a semiconductive material over a top surface of the plurality of fins. An etch stop layer is formed over the semiconductive material, and an insulating material is disposed over the etch stop layer. The insulating material and a portion of the etch stop layer are removed from over the plurality of fins. Forming the semiconductive material or forming the etch stop layer are controlled so that removing the portion of the etch stop layer does not remove the etch stop layer between a widest portion of the semiconductive material over the plurality of fins.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece comprising a plurality of fins;

forming a semiconductive material over a top surface of the plurality of fins;

forming an etch stop layer over the semiconductive material;

disposing an insulating material over the etch stop layer; and

removing the insulating material and a portion of the etch stop layer from over the plurality of fins, wherein forming the semiconductive material or forming the etch stop layer are controlled so that removing the portion of the etch stop layer does not remove the etch stop layer between a widest portion of the semiconductive material over the plurality of fins.

2. The method according to claim 1, wherein both forming the semiconductive material and forming the etch stop layer are controlled.

3. The method according to claim 1, wherein forming the semiconductive material is controlled by controlling a space between the widest portions of the semiconductive material over the plurality of fins.

4. The method according to claim 1, wherein forming the etch stop layer is controlled by controlling a thickness of the etch stop layer.

5. The method according to claim 1, wherein forming the etch stop layer comprises forming a material having an etch selectivity to the insulating material.

6. The method according to claim 5, wherein forming the etch stop layer comprises forming SiN, SiON, SiC, or SiOC.

7. The method according to claim 1, wherein removing the portion of the etch stop layer comprises leaving at least about 15 nm of the etch stop layer over the widest portion of the semiconductive material over the plurality of fins.

8. The method according to claim 1, wherein the plurality of fins comprise fins of a fin field effect transistor (FinFET).

9. A method of manufacturing a semiconductor device, the method comprising:

providing a workpiece;

forming a plurality of fins over the workpiece;

epitaxially growing a semiconductive material over a top surface of each of the plurality of fins;

forming an etch stop layer over the semiconductive material;

disposing an insulating material over the etch stop layer;

removing the insulating material and a portion of the etch stop layer over the plurality of fins; and

forming a conductive material over the plurality of fins, wherein forming the semiconductive material or forming the etch stop layer are controlled so that removing the portion of the etch stop layer does not remove the etch stop layer between a widest portion of the semiconductive material over the plurality of fins.

10. The method according to claim 9, wherein epitaxially growing the semiconductive material comprises forming a semiconductive material that is non-merged over the top surfaces of the plurality of fins.

11. The method according to claim 9, wherein removing the portion of the etch stop layer comprises exposing a top portion of the semiconductive material over the top surface of each of the plurality of fins.

12. The method according to claim 9, wherein forming the conductive material comprises forming a contact.

13. The method according to claim 12, wherein forming the contact comprises forming a slot contact or a plug contact.

14. The method according to claim 9, wherein manufacturing the semiconductor device comprises forming a transistor.

15. A method of manufacturing a transistor, the method comprising:

providing a workpiece;

forming a plurality of fins over the workpiece;

epitaxially growing a non-merged semiconductive material over a top surface of each of the plurality of fins, the semiconductive material being wider proximate a central region than proximate a top surface of the semiconductive material;

forming an etch stop layer over the semiconductive material, wherein a portion of the etch stop layer is formed below the wider central regions of the semiconductive material;

disposing an insulating material over the etch stop layer;

etching away the insulating material and a top portion of the etch stop layer over the plurality of fins; and

forming a conductive material over the plurality of fins to form a contact, wherein forming the semiconductive material or forming the etch stop layer are controlled so that removing the top portion of the etch stop layer does not remove the etch stop layer between the wider central regions of the semiconductive material over the plurality of fins.

16. The method according to claim 15, wherein forming the etch stop layer comprises forming apertures in the etch stop layer between the semiconductive material over the plurality of fins, and wherein etching away the top portion of the etch stop layer does not reach the apertures in the etch stop layer.

17. The method according to claim 15, wherein a thickness of the etch stop layer is at least half of a minimum space between the semiconductive material over the plurality of fins.

18. The method according to claim 15, wherein forming the etch stop layer comprises forming a first etch stop layer, and wherein disposing the insulating material comprises forming a first inter-level dielectric (ILD) over the first etch stop layer, forming a second etch stop layer over the first ILD, and forming a second ILD over the second etch stop layer.

19. The method according to claim 15, wherein disposing the insulating material comprises forming a first insulating material, further comprising forming a second insulating material between the plurality of fins, after forming the plurality of fins over the workpiece.

20. The method according to claim 15, wherein forming the plurality of fins comprises forming a channel, a drain region, or a source region of the transistor.