Method for fabricating a non-volatile memory device

• US 8,377,782 B2
• Filed: 12/27/2011
• Issued: 02/19/2013
• Est. Priority Date: 10/10/2007
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Hong, Young Ok, Lee, Myung Shik
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US13/338,048
• Publication Number:
  US 20120094451A1
• Time in Patent Office: 420 Days
• Field of Search: 438/197, 438/264, 438/266, 438/286, 438/288, 438/302, 438/303
• US Class Current: 438/286
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for fabricating a non-volatile memory device with asymmetric source/drain junctions, wherein a gate stack is formed on a semiconductor substrate, and impurity ions are implanted at a predetermined angle to form a source/drain junction in the semiconductor substrate. Thermal treatment of the semiconductor substrate forms an asymmetrically disposed source/drain junction between adjacent gate stacks.

Claims

1. A method for fabricating a non-volatile memory device comprising:

forming gate stacks on a semiconductor substrate;

implanting impurity ions at a predetermined tilt angle in the semiconductor substrate wherein each gate stack is laterally spaced at a predetermined interval, wherein a portion of the semiconductor substrate is disposed in a space between adjacent ones of the gate stacks and no gate stack structures are disposed on the portion of the semiconductor device, and wherein each gate stack comprises a tunneling layer disposed on the semiconductor substrate, a charge trapping layer disposed on the tunneling layer, a blocking layer disposed on the charge trapping layer to block charge transfer, and a control gate disposed on the blocking layer; and

performing a thermal treatment process to form source/drain junctions between adjacent gate stacks,

wherein the source/drain junctions each comprise a first edge portion that overlaps an edge of the one of the plurality of gate stacks and a second edge portion on a side opposite the first edge portion, wherein the second edge portion does not overlap the one of the plurality of gate stacks or an adjacent one of the plurality of gate stacks to be apart from the opposite edge of the gate stacks, and the second edge portion overlaps the portion of the semiconductor substrate in which no gate stack structures are disposed.

2. The method of claim 1, wherein the charge trapping layer comprises a single layer or a multi layer.

3. The method of claim 1, wherein the predetermined tilt angle is approximately 4°

to approximately 7°

.

4. The method of claim 1, comprising implanting the impurity ions on the semiconductor substrate with an energy of approximately 5 KeV to approximately 50 KeV and a dose of approximately 1×

10¹³ atom/cm² to approximately 1×

10¹⁴ atom/cm².

5. The method of claim 1, comprising performing the thermal treatment process is performed at a temperature between approximately 700°

C. and approximately 1000°

C.

6. The method of claim 1, wherein forming the gate stacks comprises:

forming a tunneling layer and a conductive layer for a floating gate on the semiconductor substrate, wherein each gate stack is laterally spaced at a predetermined interval, wherein a portion of the semiconductor substrate is disposed in a space between adjacent ones of the gate stacks and no gate stack structures are disposed on the portion of the semiconductor device, wherein each gate stack comprises a tunneling layer disposed on the semiconductor substrate, a floating gate on the tunneling layer, an interlayer insulating layer disposed on the floating gate, and a control gate disposed on the interlayer insulating layer;

implanting impurity ions at a predetermined tilt angle in the semiconductor substrate; and

performing a thermal treatment process to form source/drain junctions between adjacent gate stacks,

wherein the source/drain junctions each comprise a first edge portion that overlaps an edge of the one of the plurality of gate stacks and a second edge portion on a side opposite the first edge portion, wherein the second edge portion does not overlap the one of the plurality of gate stacks or an adjacent one of the plurality of gate stacks to be apart from the opposite edge of the gate stacks, and the second edge portion overlaps the portion of the semiconductor substrate in which no gate stack structures are disposed.

7. The method of claim 6, wherein the predetermined tilt angle is approximately 4°

to approximately 7°

.

8. The method of claim 6, comprising implanting the impurity ions on the semiconductor substrate with an energy of approximately 5 KeV to approximately 50 KeV and a dose of approximately 1×

10¹³ atom/cm² to approximately 1×

10¹⁴ atom/cm².

9. The method of claim 6, comprising performing the thermal treatment process at a temperature between approximately 700°

C. and approximately 1000°

C.

10. The method of claim 6, wherein forming the gate stacks comprises:

forming a tunneling layer and a conductive layer for a floating gate on the semiconductor substrate;

patterning the conductive layer and exposing the semiconductor substrate on a device isolation region to form the floating gate;

etching an exposed area of the semiconductor substrate to form a trench;

filling the trench with an insulating layer to form a device isolation layer;

forming an interlayer insulating layer that surrounds the floating gate; and

forming a control gate on the interlayer insulating layer.