Method for reducing punch-through in a transistor device

• US 8,377,783 B2
• Filed: 09/30/2010
• Issued: 02/19/2013
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: SuVolta, Inc.
• Inventors: Shifren, Lucian, Ema, Taiji
• Primary Examiner(s): Mandala, Michelle
• Assistant Examiner(s): WHITE, SHAKA SHAKAR
• Application Number:
  US12/895,695
• Publication Number:
  US 20120083080A1
• Time in Patent Office: 873 Days
• Field of Search: 257/376, 257/E21.443
• US Class Current: 438/289
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

Abstract

Punch-through in a transistor device is reduced by forming a well layer in an implant region, forming a stop layer in the well layer of lesser depth than the well layer, and forming a doped layer in the stop layer of lesser depth than the stop layer. The stop layer has a lower concentration of impurities than the doped layer in order to prevent punch-through without increasing junction leakage.

Claims

1. A method for reducing punch-through in a transistor device, comprising:

forming a first well layer in a first implant region for a PMOS device using a directional Phosphorous implant in an energy range of 100 to 400 keV and a concentration range of 1e12/cm² to 2e13/cm²;

forming a first stop layer in the first well layer of lesser depth than the first well layer using an Arsenic dopant implant in an energy range of 20 to 100 keV and a concentration range of 1e12/cm² to 1e13/cm²;

forming a first doped layer in the first stop layer of lesser depth than the first stop layer using an Arsenic implant in an energy range of 1 to 10 keV and a concentration range of 5e12/cm² to 1e14/cm², the first stop layer having a lower concentration of dopant impurities than the first doped layer;

wherein the first stop layer and first doped layer implant conditions are selected so that the first doped layer is above and in contact with the first stop layer;

forming an epitaxial layer on the first doped layer, wherein the epitaxial layer is undoped;

forming a resulting transistor device, the resulting transistor device employing the undoped epitaxial layer;

wherein the undoped epitaxial layer is above and in contact with the first doped layer, and wherein the first stop layer, the first doped layer, and the undoped epitaxial layer comprise a three-layer stack; and

forming a source region and a drain region, the source and drain regions penetrating the three-layer stack through the first doped layer and partially into the first stop layer.

4. The method of claim 1, wherein the first well layer is directly underneath and in contact with the first stop layer.

2. A method for reducing punch-through in a transistor device, comprising:

forming a well layer in an implant region for a NMOS device using a directional Boron implant in an energy range of 50 to 200 keV and a concentration range of 1e12/cm² to 2e13/cm², a pre-amorphous Germanium implant at in an energy range of 20 to 80 keV and a concentration range of 1e14/cm² to 5e15/cm², and a Carbon implant in an energy range of 1 to 10 keV and a concentration range of 5e13/cm² to 5e15/cm²;

forming a stop layer in the well layer of lesser depth than the well layer using a Boron implant in an energy range of 5 to 40 keV and a concentration range of 1e12/cm² to 1e13/cm²; and

forming a doped layer in the stop layer of lesser depth than the stop layer using a Boron implant in an energy range of 0.5 to 8 keV and a concentration range of 5e12/cm² to 1e14/cm², the stop layer having a lower concentration of dopant impurities than the doped layer;

wherein the stop layer and the doped layer implant conditions are selected so that the doped layer is above and in contact with the stop layer;

forming an epitaxial layer on the doped layer, wherein the epitaxial layer is undoped;

forming a resulting transistor device, the resulting transistor device employing the undoped epitaxial layer;

wherein the undoped epitaxial layer is above and in contact with the doped layer, and wherein the stop layer, the doped layer and the undoped epitaxial layer comprise a three-layer stack; and

forming a source region and a drain region, the source and drain regions penetrating the three-layer stack through the doped layer and partially into the stop layer.

5. The method of claim 2, wherein the well layer is directly underneath and in contact with the stop layer.

3. A method for reducing punch-through in a transistor device, comprising:

forming a first well layer in a first implant region for a PMOS device using a directional Phosphorous implant in an energy range of 100 to 400 keV and a concentration range of 1e12/cm² to 2e13/cm²;

forming a first stop layer in the first well layer of lesser depth than the first well layer using an Arsenic dopant implant in an energy range of 20 to 100 keV and a concentration range of 1e12/cm² to 1e13/cm²; and

forming a first doped layer in the first stop layer of lesser depth than the first stop layer using an Arsenic implant in an energy range of 1 to 10 keV and a concentration range of 5e12/cm² to 1e14/cm², the first stop layer having a lower concentration of dopant impurities than the first doped layer;

wherein the first stop layer and first doped layer implant conditions are selected so that the first doped layer is above and in contact with the first stop layer;

forming a second well layer in a second implant region for a NMOS device using a directional Boron implant in an energy range of 50 to 200 keV and a concentration range of 1e12/cm² to 2e13/cm², a pre-amorphous Germanium implant in an energy range of 20 to 80 keV and a concentration range of 1e14/cm² to 5e15/cm², and a Carbon implant in an energy range of 1 to 10 keV and a concentration range of 5e13/cm² to 5e15/cm²;

forming a second stop layer in the second well layer of lesser depth than the second well layer using a Boron implant in an energy range of 5 to 40 keV and a concentration range of 1e12/cm² to 1e13/cm²; and

forming a second doped layer in the second stop layer of lesser depth than the second stop layer using a Boron implant in an energy range of 0.5 to 8 keV and a concentration range of 5e12/cm² to 1e14/cm², the second stop layer having a lower concentration of dopant impurities than the second doped layer;

wherein the second stop layer and second doped layer implant conditions are selected so that the second doped layer is above and in contact with the second stop layer;

forming a first epitaxial layer on the first doped layer, wherein the first epitaxial layer is undoped;

forming a second epitaxial layer on the second doped layer, wherein the second epitaxial layer is undoped;

wherein the first stop layer, the first doped layer, and the first epitaxial layer comprise a first three-layer stack;

wherein the second stop layer, the second doped layer, and the second epitaxial layer comprise a second three-layer stack;

forming a first source region and a first drain region, the first source and drain regions penetrating the first three-layer stack through the first doped layer into the first stop layer;

forming a second source region and a second drain region, the second source and drain regions penetrating the second three-layer stack through the second doped layer into the second stop layer;

forming resulting transistor devices, the resulting transistor devices separately employing the undoped first epitaxial layer and the undoped second epitaxial layer.

6. The method of claim 3, wherein:

the first well layer is directly underneath and in contact with the first stop layer; and

the second well layer is directly underneath and in contact with the second stop layer.