Method of forming electrical connections

• US 8,377,816 B2
• Filed: 04/27/2010
• Issued: 02/19/2013
• Est. Priority Date: 07/30/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Chung-Shi, Jeng, Shin-Puu, Lii, Mirng-Ji, Yu, Chen-Hua
• Primary Examiner(s): Wagner, Jenny L
• Application Number:
  US12/768,025
• Publication Number:
  US 20110027944A1
• Time in Patent Office: 1,029 Days
• Field of Search: 438612-614
• US Class Current: 438/613
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A method of forming electrical connections to a semiconductor wafer. A semiconductor wafer comprising an insulation layer is provided. The insulation layer has a surface. A patterned mask layer is formed over the surface of the insulation layer. The patterned mask layer exposes portions of the surface of the insulation layer through a plurality of holes. The portions of the plurality of holes are filled with a metal material comprising copper to form elongated columns of the metal material. The elongated columns of the metal material have a sidewall surface. The patterned mask layer is removed to expose the sidewall surface of the elongated columns of the metal material. A protection layer is formed on the exposed sidewall surface of the elongated columns of the metal material.

Claims

1. A method of forming electrical connections to a semiconductor wafer, the method comprising:

providing a semiconductor wafer comprising an insulation layer, the insulation layer having a surface;

forming an elongated column of a metal material comprising copper, protruding from the surface of the insulation layer, wherein the elongated columns of the metal material have a sidewall surface;

forming a protection layer by an electroless plating process on the sidewall surface of the elongated columns of the metal material, wherein the protection layer comprises Sn; and

covering a top surface of the elongated columns with a conductive material by an electroless plating process, the conductive material being discontinuous with the protection layer.

2. The method of claim 1, further comprising:

forming the protection layer on a top surface of the elongated column of the metal material.

3. The method of claim 1, wherein

the covering the top surface of the elongated columns of the metal material with a conductive material occurs before the step of forming the protection layer.

4. The method of claim 1, wherein the step of forming the protection layer comprises immersing the elongated column of the metal material in an electroless plating solution containing Sn.

5. The method of claim 4, wherein the electroless plating solution is at a temperature in the range of between 25°

C. and 100°

C.

6. The method of claim 4, wherein the electroless plating solution contains Sn at a concentration in the range of between 2 g/liter and 50 g/liter.

7. The method of claim 3, wherein the conductive material comprises Ni, Sn, Au or Pd.

8. The method of claim 3, wherein the semiconductor wafer comprises an integrated circuit and the elongated column of the metal material electrically contacts with the integrated circuit.

9. A method of forming electrical connections to a semiconductor wafer, the method comprising:

providing a semiconductor wafer comprising an integrated circuit;

forming an insulation layer having a surface over the semiconductor wafer, wherein a conductive path is underlying the insulation layer and electrically contacts with the integrated circuit;

forming an elongated column of metal material comprising copper, having sidewalls, protruding from the surface of the insulation layer, wherein the elongated column of metal material contacts with the conductive path through the insulation layer; and

forming a discontinuous protection layer on the sidewalls by exposing the elongated column of metal material to a gaseous precursor containing Sn, Si or Ge that reacts with copper in the metal material.

10. The method of claim 9, further comprising:

forming the protection layer on a top surface of the elongated column of metal material.

11. The method of claim 9, further comprising:

covering a top surface of the elongated column of metal material with a conductive material before the step of forming the protection layer.

12. The method of claim 9, wherein the gaseous precursor is at a pressure in the range of between 1 mTorr and 10 Torr.

13. The method of claim 9, wherein the gaseous precursor is under at a temperature in the range of between 100 and 400°

C.

14. The method of claim 9, wherein the gaseous precursor comprises SnCl₄, SnH₄, GeH₄, Ge2H₆, SiH₄, Si₂H₆, Sn(nBu)₄, SnMe₄, SnEt₄, or Sn(iPr)₄.

15. The method of claim 9, wherein the protection layer comprises Sn, Si or Ge.

16. A method of forming a semiconductor device, the method comprising:

providing a semiconductor chip;

forming an insulation layer over the semiconductor chip, the insulation layer having a surface;

forming an elongated column of metal material comprising copper, having sidewalls, protruding from the surface of the insulation layer;

forming a discontinuous protection layer on the sidewalls by exposing the elongated column of metal material to a gaseous precursor containing Sn, Si or Ge that reacts with copper in the metal material; and

bonding a semiconductor component onto the elongated column of metal material of the semiconductor chip, the semiconductor component electrically connecting the semiconductor chip.

17. The method of claim 16, further comprising:

forming the protection layer on a top surface of the elongated column of metal material.

18. The method of claim 16, further comprising:

covering a top surface of the elongated column of metal material with a conductive material before the step of forming the protection layer.

19. The method of claim 16, wherein the gaseous precursor comprises at least of SnCl₄, SnH₄, GeH₄, Ge2H₆, SiH₄, Si₂H₆, Sn(nBu)₄, SnMe₄, SnEt₄, or Sn(iPr)₄.

20. The method of claim 16, further comprising:

filling an underfill between a gap defined between the semiconductor chip and the semiconductor component.