Circuit architecture for the parallel supplying during electric or electromagnetic testing of a plurality of electronic devices integrated on a semiconductor wafer

• US 8,378,346 B2
• Filed: 02/07/2011
• Issued: 02/19/2013
• Est. Priority Date: 08/07/2008
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pagani, Alberto
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): HALL, VICTORIA KATHLEEN
• Application Number:
  US13/022,419
• Publication Number:
  US 20110186838A1
• Time in Patent Office: 743 Days
• Field of Search: 257/48, 257/202, 257/203, 257/207, 257/208, 257/210, 257/211, 257/620, 257/E23.01, 257/E21.531, 438/17, 438/14, 438/18, 324/252, 324/260, 324/537, 3247501-76206
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group.

Claims

1. A semiconductor wafer configured for wafer level testing, comprising:

a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges;

separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other;

a conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group;

interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; and

an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line wherein said internal portion includes crossing connections coupled between respective pairs of the interconnection pads.

2. The semiconductor wafer according to claim 1, wherein each electronic device of said group comprises a power supply pad at one of the edges of the electronic device, the power supply pad being connected with the external portion of said conductive grid.

3. The semiconductor wafer according to claim 1, wherein each electronic device of said group comprises a plurality of power supply pads at the edges of the electronic device, each power supply pad being connected to the external portion of said conductive grid.

4. The semiconductor wafer according to claim 2, wherein said external portion includes a conductive second bridging connection coupled between power supply pads of adjacent electronic devices of the group.

5. The semiconductor wafer according to claim 1, wherein one of the electronic devices of the group includes two interconnection pads and said internal portion includes an electric connection between the interconnection pads.

9. The semiconductor wafer according to claim 1, wherein said external portion and said internal portion of said conductive grid are orthogonal to each other.

6. A semiconductor wafer configured for wafer level testing, comprising:

a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges;

separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other;

conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group;

interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group;

an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line; and

an insulating layer positioned on said first separation scribe line, wherein the first and second interconnection pads extend through the insulating layer, the external passivation layer is positioned on said insulating layer, and the conductive first bridging connection extends on the insulating and external passivation layers and between the respective interconnection pads of the two adjacent electronic devices.

7. A semiconductor wafer configured for wafer level testing, comprising:

a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges;

separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other;

a conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group;

interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; and

an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line, wherein;

the external portion of the conductive grid includes a conductive line extending longitudinally within said first separation scribe line;

the conductive first bridging connection extends between the first interconnection pad and the conductive line; and

the conductive grid includes a conductive second bridging connection extending between the second interconnection pad and the conductive line, the first and second interconnection pads being electrically coupled to each other by the conductive first bridging connection and conductive second bridging connection and the conductive line.

8. A semiconductor wafer configured for wafer level testing, comprising:

a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges;

separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other;

a conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group;

interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; and

an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line, wherein said interconnection pads comprise power supply dummy pads and signal dummy pads.

10. A semiconductor wafer configured for wafer level testing, comprising:

a plurality of electronic devices integrated on the semiconductor wafer wherein, said electronic devices have edges;

separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other;

a conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group;

interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; and

an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line, wherein said external portion includes a set of conductive lines extending lengthwise in the scribe lines, respectively.

11. The semiconductor wafer according to claim 10, wherein the set of conductive lines includes first conductive lines extending substantially parallel to each other and second conductive lines extending substantially parallel to each other and substantially orthogonally to the first conductive lines, said first conductive lines being insulated from the second conductive lines at crossover points.

12. A semiconductor wafer configured for wafer level testing, comprising:

a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges;

separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other;

a conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group;

interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group;

an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line; and

an insulating layer extending within and at least partially filling said first separation scribe line, wherein;

the external portion includes a conductive line buried in said insulating layer;

the conductive first bridging connection and the external passivation layer are positioned on said insulating layer; and

the external portion includes a connection via extending through the insulating and external passivation layers and connecting the conductive first bridging connection to said buried conductive line.

13. A semiconductor wafer configured for wafer level testing, comprising:

a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges;

separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other;

a conductive grid interconnecting a group of said electronic devices and having an external ion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group;

interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; and

an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line, wherein the external portion includes a fuse link.

14. A method comprising:

forming scribe lines on a semiconductor wafer;

forming a plurality of electronic devices integrated on said semiconductor wafer and separated from each other by said scribe lines, the electronic devices including first and second electronic devices;

forming an external passivation layer positioned on the scribe lines and on the electronic devices;

forming a respective plurality of interconnection pads on each electronic device respectively, wherein the interconnection pads include first and second interconnection pads on the first and second electronic devices, respectively, and the scribe lines include a first scribe line positioned between the first and second interconnection pads;

forming a conductive grid on said semiconductor wafer, said forming said conductive grid including;

forming an external portion of said conductive grid along said scribe lines;

forming an internal portion of said conductive grid within said electronic devices; and

connecting one of the interconnection pads of each electronic device to one of the interconnection pads of adjacent one of the electronic devices and to said conductive grid, forming power supply lines common to said electronic devices, wherein the connecting includes forming a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first scribe line; and

supplying a voltage to all of said electronic devices simultaneously said conductive grid.

15. The method of claim 14 wherein forming said internal portion comprises electrically connecting two interconnection pads of a same electronic device of the electronic devices.

16. The method of claim 14, comprising simultaneously testing said electronic devices.

17. A semiconductor wafer configured for wafer level testing, comprising:

a plurality of electronic devices integrated on the semiconductor wafer, each electronic device including a power supply pad;

scribe lines separating the electronic devices from each other;

a conductive grid of conductive lines extending lengthwise in the scribe lines, wherein the conductive grid of conductive lines includes first conductive lines extending substantially parallel to each other and second conductive lines extending substantially parallel to each other and substantially orthogonally to the first conductive lines;

a plurality of bridging connectors electrically connecting the conductive grid to the power supply pad of each of the electronic devices; and

an external passivation layer positioned on the scribe lines and on the electronic devices, wherein the electronic devices include first and second electronic devices, the scribe lines include a first scribe line positioned between the first and second electronic devices, the bridging connectors includes a first bridging connector electrically coupled between the power supply pad of the first electronic device and the power supply pad of the second electronic device, and the first bridging connector extends on an external surface of a portion of the external passivation layer that is positioned on the first scribe line.

18. The semiconductor wafer according to claim 17, wherein the first conductive lines are insulated from the second conductive lines at crossover points at which one of the first conductive lines crosses one of the second conductive lines.

19. The semiconductor wafer according to claim 17, further comprising:

an insulating layer extending within and at least partially filling said scribe lines, wherein the external passivation layer covers the insulating layer and the conductive lines are buried in said insulating layer, the bridging connectors extending on said insulating layer and on at least one of the devices; and

a plurality of connection vias extending through the insulating layer and the external passivation layer and respectively connecting respective bridging connectors to respective conductive lines.