Circuit architecture for the parallel supplying during electric or electromagnetic testing of a plurality of electronic devices integrated on a semiconductor wafer
First Claim
1. A semiconductor wafer configured for wafer level testing, comprising:
- a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges;
separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other;
a conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group;
interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; and
an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line wherein said internal portion includes crossing connections coupled between respective pairs of the interconnection pads.
1 Assignment
0 Petitions
Accused Products
Abstract
A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group.
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Citations
19 Claims
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1. A semiconductor wafer configured for wafer level testing, comprising:
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a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges; separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other; a conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group; interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; and an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line wherein said internal portion includes crossing connections coupled between respective pairs of the interconnection pads. - View Dependent Claims (2, 3, 4, 5, 9)
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6. A semiconductor wafer configured for wafer level testing, comprising:
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a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges; separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other; conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group; interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line; and an insulating layer positioned on said first separation scribe line, wherein the first and second interconnection pads extend through the insulating layer, the external passivation layer is positioned on said insulating layer, and the conductive first bridging connection extends on the insulating and external passivation layers and between the respective interconnection pads of the two adjacent electronic devices.
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7. A semiconductor wafer configured for wafer level testing, comprising:
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a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges; separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other; a conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group; interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; and an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line, wherein; the external portion of the conductive grid includes a conductive line extending longitudinally within said first separation scribe line; the conductive first bridging connection extends between the first interconnection pad and the conductive line; and the conductive grid includes a conductive second bridging connection extending between the second interconnection pad and the conductive line, the first and second interconnection pads being electrically coupled to each other by the conductive first bridging connection and conductive second bridging connection and the conductive line.
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8. A semiconductor wafer configured for wafer level testing, comprising:
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a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges; separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other; a conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group; interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; and an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line, wherein said interconnection pads comprise power supply dummy pads and signal dummy pads.
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10. A semiconductor wafer configured for wafer level testing, comprising:
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a plurality of electronic devices integrated on the semiconductor wafer wherein, said electronic devices have edges; separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other; a conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group; interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; and an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line, wherein said external portion includes a set of conductive lines extending lengthwise in the scribe lines, respectively. - View Dependent Claims (11)
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12. A semiconductor wafer configured for wafer level testing, comprising:
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a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges; separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other; a conductive grid interconnecting a group of said electronic devices and having an external portion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group; interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line; and an insulating layer extending within and at least partially filling said first separation scribe line, wherein; the external portion includes a conductive line buried in said insulating layer; the conductive first bridging connection and the external passivation layer are positioned on said insulating layer; and the external portion includes a connection via extending through the insulating and external passivation layers and connecting the conductive first bridging connection to said buried conductive line.
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13. A semiconductor wafer configured for wafer level testing, comprising:
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a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges; separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other; a conductive grid interconnecting a group of said electronic devices and having an external ion external to the electronic devices of said group and an internal portion internal to the electronic devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the electronic devices of said group; interconnection pads positioned on the electronic devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the electronic devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group; and an external passivation layer positioned on the separation scribe lines and on the electronic devices of said group, wherein the interconnection pads include first and second interconnection pads, the separation scribe lines include a first separation scribe line positioned between the first and second interconnection pads, and the conductive grid includes a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first separation scribe line, wherein the external portion includes a fuse link.
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14. A method comprising:
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forming scribe lines on a semiconductor wafer; forming a plurality of electronic devices integrated on said semiconductor wafer and separated from each other by said scribe lines, the electronic devices including first and second electronic devices; forming an external passivation layer positioned on the scribe lines and on the electronic devices; forming a respective plurality of interconnection pads on each electronic device respectively, wherein the interconnection pads include first and second interconnection pads on the first and second electronic devices, respectively, and the scribe lines include a first scribe line positioned between the first and second interconnection pads; forming a conductive grid on said semiconductor wafer, said forming said conductive grid including; forming an external portion of said conductive grid along said scribe lines; forming an internal portion of said conductive grid within said electronic devices; and connecting one of the interconnection pads of each electronic device to one of the interconnection pads of adjacent one of the electronic devices and to said conductive grid, forming power supply lines common to said electronic devices, wherein the connecting includes forming a conductive first bridging connection electrically coupled between the first and second interconnection pads and extending on an external surface of a portion of the external passivation layer that is positioned on the first scribe line; and supplying a voltage to all of said electronic devices simultaneously said conductive grid. - View Dependent Claims (15, 16)
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17. A semiconductor wafer configured for wafer level testing, comprising:
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a plurality of electronic devices integrated on the semiconductor wafer, each electronic device including a power supply pad; scribe lines separating the electronic devices from each other; a conductive grid of conductive lines extending lengthwise in the scribe lines, wherein the conductive grid of conductive lines includes first conductive lines extending substantially parallel to each other and second conductive lines extending substantially parallel to each other and substantially orthogonally to the first conductive lines; a plurality of bridging connectors electrically connecting the conductive grid to the power supply pad of each of the electronic devices; and an external passivation layer positioned on the scribe lines and on the electronic devices, wherein the electronic devices include first and second electronic devices, the scribe lines include a first scribe line positioned between the first and second electronic devices, the bridging connectors includes a first bridging connector electrically coupled between the power supply pad of the first electronic device and the power supply pad of the second electronic device, and the first bridging connector extends on an external surface of a portion of the external passivation layer that is positioned on the first scribe line. - View Dependent Claims (18, 19)
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Specification