High aspect-ratio PN-junction and method for manufacturing the same

• US 8,378,382 B2
• Filed: 12/30/2004
• Issued: 02/19/2013
• Est. Priority Date: 12/30/2004
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Wu, Chao-I, Lee, Ming Hsiu
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): CHIU, TSZ K
• Application Number:
  US11/027,807
• Publication Number:
  US 20060145307A1
• Time in Patent Office: 2,973 Days
• Field of Search: 257/E23.147, 257/930, 257/929, 257/51, 257/653, 257/544, 257/550, 257/212, 257/530, 257/104, 257/107, 257/119, 257/E29.327, 438/131, 438/467, 438/600, 438/242, 438/212, 438/268, 438/270
• US Class Current: 257/104
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes
• CPC Class Codes: H10B 99/16 comprising memory cells having diodes

Abstract

A semiconductor device having high-aspect-ratio PN-junctions is provided. The semiconductor device includes a conducting layer. The semiconductor device further includes a plurality of first doped regions formed over the conducting layer. The sidewalls of the doped regions are doped to form PN-junctions. The semiconductor device also includes a plurality of second doped regions over the first doped regions.

Claims

1. A semiconductor device comprising:

a conducting layer;

a plurality of first regions associated with a first dopant over the conducting layer, wherein each of the first regions has at least two sidewall spacers of a second dopant and the at least two sidewalk comprise four sidewalls and the sidewall spacers are in direct contact with first regions to form PN-junctions; and

a plurality of second regions associated with the second dopant formed over the first regions to position the first regions between the conducting layer and the second regions.

2. The semiconductor device of claim 1, wherein the first regions are P-regions and the second regions are N-regions.

3. The semiconductor device of claim 1, wherein the first regions are N-regions and the second regions are P-regions.

4. The semiconductor device of claim 1, further comprising:

a plurality of gaps defined between the first regions and filled with isolation material.

5. The semiconductor device of claim 4, wherein the isolation material is composed of oxide.

6. The semiconductor device of claim 1, further comprising:

a plurality of gaps defined between the second regions; and

a plurality of regions disposed within the gaps defined between the second regions and filled with isolation material.

7. The semiconductor device of claim 1, wherein the first dopant is of N+ type.

8. A semiconductor device comprising:

a conducting layer;

a plurality of regions associated with a first dopant formed on the upper surface of the conducting layer;

an isolation layer formed over the plurality of regions associated with the first dopant, the isolation-layer being formed over at least two sidewalls of the plurality of regions associated with the first dopant, is doped with a second dopant, wherein the isolation layer covers the upper surface of the regions associated with the first dopant and the upper surface of the conducting layer in between the regions associated with the first dopant; and

a plurality of regions associated with the second dopant formed over the regions associated with the first dopant such that the isolation-layer separates the plurality of regions associated with the first dopant and corresponding regions associated with the second dopant, wherein each of the plurality of regions associated with the first dopant corresponds to one of the plurality of regions associated with the second dopant to form a PIN-junction that is operable as a memory cell.

9. The semiconductor device of claim 8, further comprising:

a plurality of isolation regions separating both the first doped regions, and the second doped regions.

10. The semiconductor device of claim 8, wherein the plurality of regions associated with the first dopant are P-regions and the plurality of regions associated with the second dopant are N-regions.

11. The semiconductor device of claim 8, wherein the plurality of regions associated with the first dopant are N-regions and the plurality of regions associated with the second dopant are P-regions.

12. The semiconductor device of claim 8, wherein the isolation regions are composed of oxides.

13. The semiconductor device of claim 8, wherein the isolation regions are composed of antifuse oxide.

14. The semiconductor device of claim 8, wherein the at least two sidewalk comprise four sidewalls.

15. A semiconductor device comprising:

a conducting layer;

a plurality of first regions associated with a first dopant over the conducting layer, wherein each of the first regions has at least two sidewall spacers of a second dopant and the at least two sidewalls comprise four sidewalk and the sidewall spacers contact to the first regions with a first dopant to increase forward current; and

a plurality of second regions associated with the second dopant formed over the first regions to position the first regions between the conducting layer and the second regions.