Semiconductor device including image sensor

• US 8,378,391 B2
• Filed: 11/03/2010
• Issued: 02/19/2013
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Yamazaki, Shunpei
• Primary Examiner(s): Ingham, John C
• Application Number:
  US12/938,400
• Publication Number:
  US 20110108836A1
• Time in Patent Office: 839 Days
• Field of Search: 257/215, 257/223, 257/225, 257/E27.13, 438/79
• US Class Current: 257/225
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 31/095 comprising amorphous semiconductors
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

A solid-state image sensor which holds a potential for a long time and includes a thin film transistor with stable electrical characteristics is provided. When the off-state current of a thin film transistor including an oxide semiconductor layer is set to 1×10⁻¹³ A or less and the thin film transistor is used as a reset transistor and a transfer transistor of the solid-state image sensor, the potential of the signal charge storage portion is kept constant, so that a dynamic range can be improved. When a silicon semiconductor which can be used for a complementary metal oxide semiconductor is used for a peripheral circuit, a high-speed semiconductor device with low power consumption can be manufactured.

Claims

1. A semiconductor device comprising a pixel portion, the pixel portion comprising:

a photoelectric conversion element portion buried in a substrate comprising a silicon semiconductor;

a transfer transistor electrically connected to the photoelectric conversion element portion;

a signal charge storage portion electrically connected to the transfer transistor;

a reset transistor electrically connected to the signal charge storage portion; and

an amplifier transistor electrically connected to the signal charge storage portion,

wherein a channel formation region of the transfer transistor comprises a first oxide semiconductor layer, a channel formation region of the reset transistor comprises a second oxide semiconductor layer, and a channel formation region of the amplifier transistor comprises the silicon semiconductor,

wherein a first conductive layer is provided over the substrate with an insulating layer interposed therebetween and in contact with the first oxide semiconductor layer and the second oxide semiconductor layer, and

wherein the signal charge storage portion includes the silicon semiconductor and the first conductive layer with the insulating layer interposed therebetween.

2. The semiconductor device according to claim 1, wherein the transfer transistor or the reset transistor is formed over the amplifier transistor.

3. The semiconductor device according to claim 1, wherein off-state current of each of the transfer transistor and the reset transistor is 1×

10<sup>−

13</sup> A or less.

4. The semiconductor device according to claim 1, wherein a carrier concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

5. The semiconductor device according to claim 1, wherein the pixel portion is electrically connected to a peripheral circuit portion including a complementary transistor having a silicon semiconductor in a channel formation region.

6. An electronic device comprising the semiconductor device according to claim 1.

7. A semiconductor device comprising a pixel portion, the pixel portion comprising:

a photoelectric conversion element portion buried in a substrate comprising a silicon semiconductor;

a transfer transistor electrically connected to the photoelectric conversion element portion;

a signal charge storage portion electrically connected to the transfer transistor;

a reset transistor electrically connected to the signal charge storage portion; and

an amplifier transistor electrically connected to the signal charge storage portion,

wherein a channel formation region of the transfer transistor comprises a first oxide semiconductor layer, a channel formation region of the reset transistor comprises a second oxide semiconductor layer, and a channel formation region of the amplifier transistor comprises the silicon semiconductor,

wherein a first conductive layer is provided over the substrate with an insulating layer interposed therebetween and in contact with the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein the signal charge storage portion includes the silicon semiconductor and the first conductive layer with the insulating layer interposed therebetween, and

wherein a second conductive layer is provided over the substrate with the insulating layer interposed therebetween and in contact with the first oxide semiconductor layer and the photoelectric conversion element portion.

8. The semiconductor device according to claim 7, wherein the transfer transistor or the reset transistor is formed over the amplifier transistor.

9. The semiconductor device according to claim 7, wherein off-state current of each of the transfer transistor and the reset transistor is 1×

10<sup>−

13</sup> A or less.

10. The semiconductor device according to claim 7, wherein a carrier concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

11. The semiconductor device according to claim 7, wherein the pixel portion is electrically connected to a peripheral circuit portion including a complementary transistor having a silicon semiconductor in a channel formation region.

12. An electronic device comprising the semiconductor device according to claim 7.

13. A semiconductor device comprising a pixel portion, the pixel portion comprising:

a photoelectric conversion element portion buried in a substrate comprising a silicon semiconductor;

a transfer transistor electrically connected to the photoelectric conversion element portion;

a signal charge storage portion electrically connected to the transfer transistor;

a reset transistor electrically connected to the signal charge storage portion; and

an amplifier transistor electrically connected to the signal charge storage portion,

wherein a channel formation region of the transfer transistor comprises a first oxide semiconductor layer, a channel formation region of the reset transistor comprises a second oxide semiconductor layer, and a channel formation region of the amplifier transistor comprises the silicon semiconductor,

wherein a first conductive layer is provided over the substrate with an insulating layer interposed therebetween and in contact with the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein the signal charge storage portion includes the silicon semiconductor and the first conductive layer with the insulating layer interposed therebetween,

wherein a second conductive layer is provided over the substrate with the insulating layer interposed therebetween and in contact with the first oxide semiconductor layer and the photoelectric conversion element portion,

wherein a third conductive layer is provided over the substrate with the insulating layer interposed therebetween and in contact with the second oxide semiconductor layer, and

wherein a field oxide film is formed in the substrate and in contact with one of a source and a drain of the amplifier transistor.

14. The semiconductor device according to claim 13, wherein the transfer transistor or the reset transistor is formed over the amplifier transistor.

15. The semiconductor device according to claim 13, wherein off-state current of each of the transfer transistor and the reset transistor is 1×

10<sup>−

13</sup> A or less.

16. The semiconductor device according to claim 13, wherein a carrier concentration in each of the first oxide semiconductor layer and the second oxide semiconductor layer is lower than 1×

10¹⁴/cm³.

17. The semiconductor device according to claim 13, wherein the pixel portion is electrically connected to a peripheral circuit portion including a complementary transistor having a silicon semiconductor in a channel formation region.

18. An electronic device comprising the semiconductor device according to claim 13.