Semiconductor device

• US 8,378,403 B2
• Filed: 06/27/2011
• Issued: 02/19/2013
• Est. Priority Date: 07/02/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US13/169,544
• Publication Number:
  US 20120001243A1
• Time in Patent Office: 603 Days
• Field of Search: 257/67, 257/68, 257/71, 257/296, 257/368, 257/E27.084, 257/E7.06
• US Class Current: 257/296
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/22 including field-effect components

Abstract

An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

Claims

1. A semiconductor device comprising:

a memory cell array comprising a first memory cell and a second memory cell;

the first memory cell comprising;

a first transistor having a first channel formation region electrically connected to a first bit line through a source or a drain of the first transistor; and

a second transistor having a second channel formation region electrically connected to a gate of the first transistor through a source or a drain of the second transistor, and

the second memory cell comprising;

a third transistor having a third channel formation region electrically connected to a second bit line through a source or a drain of the third transistor; and

a fourth transistor having a fourth channel formation region electrically connected to a gate of the third transistor through a source or a drain of the fourth transistor, and

a driver circuit associated with the first memory cell and the second memory cell,

wherein a first semiconductor material included in the first channel formation region is selected from the group consisting of silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide, and

wherein the first memory cell and the second memory cell are stacked so as to overlap at least partly with each other.

2. The semiconductor device according to claim 1, wherein the first semiconductor material is a single crystal semiconductor.

3. The semiconductor device according to claim 1, wherein a second semiconductor material included in the second to fourth channel formation regions comprises an oxide semiconductor material.

4. The semiconductor device according to claim 3, wherein the driver circuit comprises the second semiconductor material.

5. The semiconductor device according to claim 3,

wherein the driver circuit comprises the first semiconductor material, and

wherein another part of the driver circuit comprises the second semiconductor material.

6. The semiconductor device according to claim 1, wherein the driver circuit comprises the first semiconductor material.

7. The semiconductor device according to claim 1, further comprising:

a first source line electrically connected to the other of the source and the drain of the first transistor; and

a second source line electrically connected to the other of the source and the drain of the third transistor,

wherein the first source line is electrically connected to the second source line.

8. The semiconductor device according to claim 1, wherein the driver circuit comprises a selector circuit so as to select the first memory cell or the second memory cell.

9. The semiconductor device according to claim 8, wherein the first bit line and the second bit line are electrically connected to the selector circuit.

10. A semiconductor device comprising:

a first memory cell over a substrate, the first memory cell comprising;

a first transistor;

a second transistor over the first transistor; and

a first capacitor over the first transistor, and

a second memory cell over the first memory cell, the second memory cell comprising;

a third transistor;

a fourth transistor over the third transistor; and

a second capacitor over the third transistor,

wherein the second memory cell overlaps at least partly with the first memory cell,

wherein a gate of the first transistor is electrically connected to a source or a drain of the second transistor and the first capacitor,

wherein a gate of the third transistor is electrically connected to a source or a drain of the fourth transistor and the second capacitor, and

wherein a first semiconductor material included in a first channel formation region of the first transistor is selected from the group consisting of silicon, germanium, silicon germanium, silicon carbide, or gallium arsenide.

11. The semiconductor device according to claim 10, wherein the first semiconductor material is a single crystal semiconductor.

12. The semiconductor device according to claim 10, wherein a second semiconductor material included in a channel formation region of the second transistor comprises an oxide semiconductor material.

13. The semiconductor device according to claim 12, wherein a third channel formation region of the third transistor and a fourth channel formation region of the fourth transistor include the second semiconductor material.

14. The semiconductor device according to claim 13, further comprising:

a first bit line electrically connected to a source or a drain of the first transistor;

a first source line electrically connected to the other of the source and the drain of the first transistor;

a second bit line electrically connected to a source or a drain of the third transistor;

a second source line electrically connected to the other of the source and the drain of the third transistor; and

a selector circuit electrically connected to the first bit line and the second bit line,

wherein the first source line is electrically connected to the second source line, and

wherein the selector circuit selects the first bit line or the second bit line.

15. The semiconductor device according to claim 14, wherein the selector circuit includes the second semiconductor material.

16. The semiconductor device according to claim 10, further comprising:

a first bit line electrically connected to a source or a drain of the first transistor;

a first source line electrically connected to the other of the source and the drain of the first transistor;

a second bit line electrically connected to a source or a drain of the third transistor;

a second source line electrically connected to the other of the source and the drain of the third transistor; and

a selector circuit electrically connected to the first bit line and the second bit line,

wherein the first source line is electrically connected to the second source line, and

wherein the selector circuit selects the first bit line or the second bit line.