Floating gate inverter type memory cell and array

• US 8,378,407 B2
• Filed: 03/02/2010
• Issued: 02/19/2013
• Est. Priority Date: 12/07/2006
• Status: Active Grant

• Current Assignee: Tower Semiconductor Limited
• Original Assignee: Tower Semiconductor Limited
• Inventors: Audzeyeu, Mikalai, Makarevich, Yuriy, Shvedau, Siarhei, Belous, Anatoly, Pikhay, Evgeny, Dayan, Vladislav, Roizin, Yakov
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US12/715,762
• Publication Number:
  US 20100157669A1
• Time in Patent Office: 1,085 Days
• Field of Search: 257/315, 257/322, 257/E27.102
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory (NVM) cell and array includes a control capacitor, tunneling capacitor, CMOS inverter and output circuit. The CMOS inverter includes PMOS and NMOS inverter transistors. The control capacitor, tunneling capacitor and PMOS and NMOS inverter transistors share a common floating gate, which is programmed/erased by Fowler-Nordheim tunneling. The output circuit includes PMOS and NMOS select transistors. The PMOS inverter and select transistors share a common source/drain region. Similarly, the NMOS inverter and select transistors share a common source/drain region. This configuration minimizes the required layout area of the non-volatile memory cell and allows design of arrays with smaller footprints. Alternately, the tunneling capacitor may be excluded, further reducing the required layout area of the NVM cell. In this case, the NMOS inverter transistor functions as a tunneling capacitor for programming and erasing the cell, and the PMOS inverter transistor functions as a tunneling capacitor for erasing the cell.

Claims

1. A non-volatile memory cell comprising:

a control capacitor;

an inverter comprising a first inverter transistor and a second inverter transistor, wherein the control capacitor, the first inverter transistor and the second inverter transistor share a floating gate;

an output circuit comprising a first output transistor and a second output transistor, wherein the first output transistor and the first inverter transistor share a first common source/drain region, and the second output transistor and the second inverter transistor share a second common source/drain region.

2. The non-volatile memory cell of claim 1, wherein the first source/drain region is isolated from the second source/drain region.

3. The non-volatile memory cell of claim 1, wherein the first inverter transistor and the first output transistor are fabricated in a first well region having a first conductivity type.

4. The non-volatile memory cell of claim 3, wherein the second inverter transistor and the second output transistor are fabricated in a second well region having a second conductivity type, opposite the first conductivity type.

5. The non-volatile memory cell of claim 4, wherein the first well region and the second well region are located in a first deep well region having the first conductivity type.

6. The non-volatile memory cell of claim 1, further comprising a read output terminal coupled to a drain region of the first output transistor and a drain region of the second output transistor.

7. The non-volatile memory cell of claim 1, wherein the floating gate forms an electrode of the control capacitor, and wherein the control capacitor further comprises a first well region having a first conductivity type that forms a counter electrode of the control capacitor.

8. The non-volatile memory cell of claim 7, further comprising a first deep well region having a second conductivity type, opposite the first conductivity type, wherein the first well region is located in the first deep well region.

9. The non-volatile memory cell of claim 7, further comprising a tunnel capacitor, wherein the floating gate forms an electrode of the tunnel capacitor, and wherein the tunnel capacitor further comprises a second well region that forms a counter electrode of the tunnel capacitor, the second well region having the first conductivity type.

10. The non-volatile memory cell of claim 9, further comprising:

a first deep well region having a second conductivity type, opposite the first conductivity type, wherein the first well region is located in the first deep well region; and

a second deep well region having the second conductivity type, wherein the second well region is located in the second deep well region.

11. The non-volatile memory cell of claim 1, further comprising programming means for inducing Fowler-Nordheim (F-N) tunneling between the second inverter transistor and the floating gate.

12. The non-volatile memory cell of claim 11, further comprising erase means for inducing F-N tunneling between the first and second inverter transistors and the floating gate.

13. The non-volatile memory cell of claim 1, wherein:

the first inverter transistor includes a source coupled to receive a first voltage and a drain coupled to a source of the first output transistor; and

the second inverter transistor includes a source coupled to receive a second voltage, different than the first voltage, and a drain coupled to a source of the second output transistor.

14. The non-volatile memory cell of claim 13, wherein the drain of the first inverter transistor is electrically isolated from the drain of the second inverter transistor.

15. The non-volatile memory cell of claim 13, further comprising an output terminal coupled to a drain of the first output transistor and a drain of the second output transistor.

16. The non-volatile memory cell of claim 13, wherein the drain of the first inverter transistor is continuous with the source of the first output transistor, and the drain of the second inverter transistor is continuous with the source of the second output transistor.

17. An array of non-volatile memory cells comprising:

a first plurality of non-volatile memory cells that form a first row of the array, wherein each of the first plurality of non-volatile memory cells includes;

a control capacitor having a corresponding floating gate electrode;

an inverter that shares the floating gate electrode with the control capacitor; and

an output circuit coupled to the inverter;

wherein each control capacitor in the first row of the array shares a common first well region which forms a counter-electrode of the control capacitors in the first row.

18. The array of claim 17, wherein the first well region is located in a first deep well region having a conductivity type different than a conductivity type of the first well region.

19. The array of claim 17, further comprising:

a second plurality of non-volatile memory cells that form a second row of the array, wherein each of the second plurality of non-volatile memory cells includes;

a control capacitor having a corresponding floating gate electrode;

an inverter that shares the floating gate electrode with the control capacitor; and

an output circuit coupled to the inverter;

wherein each control capacitor in the second row of the array shares a common second well region which forms a counter-electrode of the control capacitors in the second row.

20. The array of claim 19, wherein each inverter includes a first PMOS inverter transistor, and each output circuit includes a first PMOS output transistor, wherein each first PMOS inverter transistor and each first PMOS output transistor is fabricated in a common n-well.

21. The array of claim 17, wherein each inverter circuit comprises a first inverter transistor and a second inverter transistor, wherein the corresponding control capacitor, the first inverter transistor and the second inverter transistor share the corresponding floating gate electrode, and wherein each output circuit comprises a first output transistor and a second output transistor, wherein the first output transistor and the first inverter transistor share a first common source/drain region, and the second output transistor and the second inverter transistor share a second common source/drain region.