Vertical trench LDMOS transistor

• US 8,378,420 B2
• Filed: 04/05/2012
• Issued: 02/19/2013
• Est. Priority Date: 12/02/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Mallikarjunaswamy, Shekar
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US13/440,929
• Publication Number:
  US 20120187481A1
• Time in Patent Office: 320 Days
• Field of Search: 257/331, 257/335, 257341-342, 257/E27.06, 438/268, 438/270, 438/283
• US Class Current: 257/341
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7817 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7823 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7825 : with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A vertical trench LDMOS transistor includes a semiconductor layer of a first conductivity type; a first trench formed in the semiconductor layer and filled with a trench dielectric and a trench gate is formed in the first trench; a body region of a second conductivity type formed in the semiconductor layer adjacent the first trench; a source region formed in the body region and adjacent the first trench; a planar gate insulated from the semiconductor layer by a second gate dielectric layer and overlying the body region; and a drain drift region formed in the semiconductor layer. The planar gate forms a lateral channel in the body region between the source region and the drain drift region, and the trench gate in the first trench forms a vertical channel in the body region along the sidewall of the first trench between the source region and the semiconductor layer.

Claims

1. A semiconductor device comprising a vertical trench LDMOS transistor, the vertical trench LDMOS transistor comprising:

a substrate of a first conductivity type;

a semiconductor layer of the first conductivity type formed on the substrate;

a first trench formed in the semiconductor layer, the first trench being filled with a trench dielectric, a trench gate being formed in the first trench and insulated from the sidewall of the first trench by a first gate dielectric layer;

a body region of a second conductivity type formed in the semiconductor layer adjacent the first trench;

a source region of the first conductivity type formed in the body region and adjacent the first trench;

a planar gate insulated from the semiconductor layer by a second gate dielectric layer and overlying the body region, the source region being formed aligned to a first edge of the planar gate;

a drain drift region of the first conductivity type formed in the semiconductor layer; and

a drain electrode formed on a backside of the substrate,

wherein the planar gate forms a lateral channel of the LDMOS transistor in the body region between the source region and the drain drift region, and the trench gate in the first trench forms a vertical channel of the LDMOS transistor in the body region along the sidewall of the first trench between the source region and the semiconductor layer.

2. The semiconductor device of claim 1, further comprising a vertical trench MOS transistor formed in a separate region of the same substrate and the same semiconductor layer, the vertical trench MOS transistor comprising:

a second trench formed in the semiconductor layer, the second trench being filled with a trench dielectric, a second trench gate being formed in the second trench and insulated from the sidewall of the second trench by a second gate dielectric layer;

a second body region of the second conductivity type formed in the semiconductor layer adjacent the second trench, the second body region extending to a depth near a bottom edge of the second trench gate formed in the second trench; and

a source region of the first conductivity type formed in the second body region and adjacent the second trench, the source region being formed in a top portion of the second body region,

wherein the vertical trench MOS transistor is formed with the substrate being a drain region, the semiconductor layer being a drain drift region, and the second trench gate being a gate electrode of the vertical trench MOS transistor.