Chip inductor with frequency dependent inductance

• US 8,378,448 B2
• Filed: 12/07/2009
• Issued: 02/19/2013
• Est. Priority Date: 03/18/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ding, Hanyi, Woods, Wayne H. Jr.
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US12/632,030
• Publication Number:
  US 20100237464A1
• Time in Patent Office: 1,170 Days
• Field of Search: 257531-535, 257/701, 257765-769, 257/777, 257/E23.002, 257/143, 257/152, 257/E25.001, 257/E27.046, 257/81, 257/85, 257/97
• US Class Current: 257/531
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 29/432 Heterojunction gate for field effect devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.

Claims

1. A non-transitory machine readable medium embodying a design structure for designing, manufacturing, or testing a design for a semiconductor structure, said design structure configured to generate a representation of said semiconductor structure in a format perceptible by humans when read by a machine, and to cause said representation to comprise:

a first element representing a dielectric material layer located on a semiconductor substrate;

a second element representing a first metal line embedded in said dielectric material layer;

a third element representing a second metal line embedded in said dielectric material layer and inductively coupled with said first metal line through a portion of said dielectric material layer; and

a fourth element representing a capacitor having a first capacitor electrode and a second capacitor electrode, wherein said first capacitor electrode is resistively connected to an end of said second metal line, and wherein said second capacitor electrode is electrically grounded.

2. The non-transitory machine readable medium of claim 1, wherein said design structure is configured to cause said representation perceptible by humans to further comprise:

a fifth element representing a first device located on said semiconductor substrate, wherein a first end of said first metal line is resistively connected to said first device; and

a sixth element representing a second device located on said semiconductor substrate, wherein a second end of said first metal line is resistively connected to said second device.

3. The non-transitory machine readable medium of claim 2, wherein said fifth element represents a signal transmitting device and said sixth element represents a signal receiving device and said second element represents a signal transmission line.

4. The non-transitory machine readable medium of claim 3, wherein said fifth element includes a seventh element representing a first signal input node structure directly connected to said first end of said first metal line and an eighth element representing a second signal input node structure directly connected to said semiconductor substrate, and wherein said sixth element includes a ninth element representing a first signal output node structure directly connected to said second end of said first metal line and a tenth element representing a second signal output node structure directly connected to said semiconductor substrate.

5. The non-transitory machine readable medium of claim 1, wherein said fourth element represents a capacitor having an impedance, wherein a magnitude of said impedance is equal to a magnitude of a sum of a first impedance due to self-inductance of said first metal line and a second impedance due to mutual inductance between said first metal line and said second metal line within a frequency range between 1 GHz and 1 THz.

6. The non-transitory machine readable medium of claim 1, wherein said second element and said third element represent metal lines that are located at a same level within said dielectric material layer and spaced from said semiconductor substrate by a same distance.

7. The non-transitory machine readable medium of claim 6, wherein, within said representation perceptible by humans, said first metal line includes a first sidewall and said second metal line includes a second sidewall, wherein said first and second sidewalls are substantially parallel to each other and abut said portion of said dielectric material layer and laterally separated from each other by a substantially constant spacing.

8. The non-transitory machine readable medium of claim 1, wherein said second element and said third element represent metal lines that are located at different levels within said dielectric material layer, wherein a vertical spacing between said first metal line and said semiconductor substrate is different from a vertical spacing between said second metal line and said semiconductor substrate within said representation perceptible by humans.

9. The non-transitory machine readable medium of claim 1, wherein said design structure is configured to cause said representation perceptible by humans to further comprise an additional element representing a grounded metal line embedded in said dielectric material layer and inductively coupled with said first metal line and grounded to said semiconductor substrate at a first end of said grounded metal line in proximity to said first device and grounded to said semiconductor substrate at a second end of said grounded metal line in proximity to said second device.

10. The non-transitory machine readable medium of claim 1, wherein said fourth element represents a metal-insulator-metal capacitor (MIMCAP) embedded in said dielectric material layer, wherein said second capacitor electrode is electrically grounded to said semiconductor substrate through at least one conductive via structure within said dielectric material layer within said representation.

11. The non-transitory machine readable medium of claim 1, wherein said fourth element represents a planar capacitor located directly on said semiconductor substrate, wherein, within said representation perceptible by humans, said second capacitor electrode is embedded in said semiconductor substrate, wherein said first capacitor electrode vertically abuts a top surface of a node dielectric located directly on said semiconductor substrate, and wherein said node dielectric comprises a same material as, and has a same thickness as, a gate dielectric of a field effect transistor located on said semiconductor substrate.

12. The non-transitory machine readable medium of claim 1, wherein said fourth element represents a deep trench capacitor located in said semiconductor substrate, wherein, within said representation perceptible by humans, said second capacitor electrode abuts and surrounds sidewalls of a deep trench and embedded in said semiconductor substrate, and wherein said first capacitor electrode and a node dielectric are located within said deep trench, and wherein said second end of said second metal line is resistively connected to said first electrode through at least one via structure within said dielectric material layer.

13. The non-transitory machine readable medium of claim 1, wherein said design structure is configured to cause said representation perceptible by humans to further comprise an additional element representing at least one semiconductor device located on said semiconductor substrate.

14. The non-transitory machine readable medium of claim 1, wherein said design structure is configured to cause said representation perceptible by humans to further comprise at least one additional element, each representing a capacitively-grounded metal line structure comprising:

an additional metal line embedded in said dielectric layer and inductively coupled with said first metal line through a portion of said dielectric material layer; and

an additional capacitor having a first additional capacitor electrode and a second additional capacitor electrode, wherein said first additional capacitor electrode is resistively connected to an end of said additional metal line, and wherein said second additional capacitor electrode is electrically grounded.