Wafer-level semiconductor device packages with electromagnetic interference shielding

• US 8,378,466 B2
• Filed: 11/19/2009
• Issued: 02/19/2013
• Est. Priority Date: 11/19/2009
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chiu, Chi-Tsung, Liao, Kuo-Hsien, Yih, Wei-Chi, Chen, Yu-Chi, Fan, Chen-Chuan
• Primary Examiner(s): Luu, Chuong A.
• Application Number:
  US12/622,393
• Publication Number:
  US 20110115060A1
• Time in Patent Office: 1,188 Days
• Field of Search: 257/660, 257/659, 257/692, 257/698, 257/662, 257/664, 257/508, 257/690, 257/708
• US Class Current: 257/660
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Described herein are wafer-level semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a semiconductor device; (2) a package body covering lateral surfaces of the semiconductor device, a lower surface of the package body and a lower surface of the semiconductor device defining a front surface; (3) a set of redistribution layers disposed adjacent to the front surface, the set of redistribution layers including a grounding element that includes a connection surface electrically exposed adjacent to at least one lateral surface of the set of redistribution layers; and (4) an EMI shield disposed adjacent to the package body and electrically connected to the connection surface of the grounding element. The grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Claims

1. A semiconductor package, comprising:

a die having an active surface;

a package body encapsulating die, the package body including an upper surface, a lower surface, and lateral surfaces disposed adjacent to a periphery of the package body, the lower surface of the package body and the active surface of the die defining a front surface;

a redistribution layer disposed on the front surface, the redistribution layer including lateral surfaces disposed adjacent to a periphery of the redistribution layer and a grounding element, the grounding element including a connection surface that is electrically exposed adjacent to at least one of the lateral surfaces of the redistribution layer; and

an electromagnetic interference shield disposed adjacent to the upper surface of the package body and the lateral surfaces of the package body, and extending along at least one of the lateral surfaces of the redistribution layer for electrical connection to the connection surface of the grounding element;

wherein the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the electromagnetic interference shield.

2. The semiconductor package of claim 1, wherein the grounding element extends between a contact pad disposed adjacent to the active surface of the die and the electromagnetic interference shield.

3. The semiconductor package of claim 2, wherein the redistribution layer includes a lower surface facing away from the die, the semiconductor package further comprises a ground electrical contact disposed adjacent to the lower surface of the redistribution layer, and the grounding element is electrically connected to the ground electrical contact.

4. The semiconductor package of claim 3, wherein the ground electrical contact is laterally disposed outside of a periphery of the die.

5. The semiconductor package of claim 1, wherein the grounding element includes a first portion and a second portion, the first portion is electrically connected to a contact pad of the die, and the second portion is disposed adjacent to the periphery of the redistribution layer and includes the connection surface.

6. The semiconductor package of claim 5, wherein the second portion is selected from the group consisting of a grounding ring, a grounding strip, and a remnant of a grounding via.

7. The semiconductor package of claim 1, wherein the electromagnetic interference shield includes a lateral portion that extends along the lateral surfaces of the redistribution layer.

8. The semiconductor package of claim 7, wherein the redistribution layer includes a lower surface, and a lower end of the lateral portion is substantially coplanar with the lower surface of the redistribution layer.

9. The semiconductor package of claim 1, wherein the lateral surfaces of the package body are substantially coplanar with respective ones of the lateral surfaces of the redistribution layer.

10. A semiconductor package, comprising:

a die including an active surface;

a package body covering the die such that the active surface of the die is electrically exposed;

a redistribution layer including;

a dielectric disposed adjacent to the active surface of the die and defining openings that are aligned with portions of the active surface of the die;

an electrical trace extending along the dielectric and electrically connected to the active surface of the die through one of the openings defined by the dielectric; and

a grounding element extending along the dielectric from the active surface of the die to a periphery of the redistribution layer, the grounding element including a lateral surface disposed adjacent to the periphery of the redistribution layer; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and electrically connected to the lateral surface of the grounding element, wherein the grounding element provides a common electrical pathway to ground electromagnetic emissions incident upon the electromagnetic interference shield and to ground the die.

11. The semiconductor package of claim 10, wherein the grounding element includes a portion that is disposed adjacent to the periphery of the redistribution layer and includes the lateral surface, and the portion is selected from the group consisting of a grounding ring, a grounding strip, and a remnant of a grounding via.

12. The semiconductor package of claim 10, wherein the grounding element is electrically connected to the active surface of the die through another one of the openings defined by the dielectric.

13. The semiconductor package of claim 10, wherein the redistribution layer includes a lower surface, and a lower end of the electromagnetic interference shield is substantially coplanar with the lower surface of the redistribution layer.

14. The semiconductor package of claim 10, wherein the electromagnetic interference shield includes a first layer and a second layer disposed adjacent to the first layer, wherein the first layer and the second layer include different electrically conductive materials.

15. The semiconductor package of claim 10, wherein:

the grounding element is electrically connected to the die; and

at least a portion of the grounding element corresponds to a remnant of a grounding via and includes the lateral surface.

16. The semiconductor package of claim 10, further comprising an electrical contact disposed outside of a periphery of the die, wherein:

the redistribution layer is disposed between the package body and the electrical contact; and

the grounding element is electrically connected to the electrical contact.

17. The semiconductor package of claim 10, wherein a lateral surface of the package body is substantially coplanar with the lateral surface of the grounding element.

18. A semiconductor package, comprising:

a die;

a molded structure encapsulating the die;

a redistribution layer disposed adjacent to the die and the molded structure, wherein a top surface of the redistribution layer is substantially coplanar with a bottom surface of the die, and wherein the redistribution layer includes a grounding portion, the grounding portion disposed adjacent to a periphery of the redistribution layer and outside of a lateral periphery of the die; and

a shield covering an external periphery of the molded structure, wherein the shield extends from the external periphery of the molded structure to the grounding portion, the redistribution layer includes a lower surface, and a lower end of the shield is substantially coplanar with the lower surface of the redistribution layer.

19. The semiconductor package of claim 18, wherein the grounding portion extends from an electrical contact included in the die to the shield.

20. The semiconductor package of claim 18, wherein:

the grounding portion is electrically connected to the die; and

at least a portion of the grounding portion corresponds to a remnant of a grounding via, wherein the remnant has a surface that is exposed at the periphery of the redistribution layer.

21. The semiconductor package of claim 18, wherein a surface of the molded structure is substantially coplanar with a surface of the grounding portion.

22. The semiconductor package of claim 18, further comprising an electrical contact disposed outside of the lateral periphery of the die, wherein:

the redistribution layer is disposed between the molded structure and the electrical contact; and

the grounding portion is electrically connected to the electrical contact.

23. The semiconductor package of claim 22, wherein the grounding portion is electrically connected to the die.

24. The semiconductor package of claim 18, wherein the shield includes a first layer and a second layer disposed adjacent to the first layer, wherein the first layer and the second layer include different electrically conductive materials.

25. The semiconductor package of claim 18, wherein lateral surfaces of the molded structure are substantially coplanar with respective ones of the lateral surfaces of the redistribution layer.