Integrated circuit packaging system with stacking option and method of manufacture thereof

• US 8,378,476 B2
• Filed: 03/25/2010
• Issued: 02/19/2013
• Est. Priority Date: 03/25/2010
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Lee, SeongMin, Mun, SeongHun, Han, Byung Joon
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US12/731,870
• Publication Number:
  US 20110233747A1
• Time in Patent Office: 1,062 Days
• Field of Search: 257/686, 257/723, 257/737, 257/778, 257/E23.003, 257/E21.099, 438/109
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/31 characterised by the arrangement or shape
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling a first integrated circuit die on the component side; coupling stacking interconnects on the component side around the first integrated circuit die; forming a package body on the component side, the first integrated circuit die, and the stacking interconnects; forming vertical insertion cavities through the package body and on the stacking interconnects; and forming a trench, in the package body, adjacent to the vertical insertion cavities for reducing a package warping stress.

Claims

1. A method of manufacture of an integrated circuit packaging system comprising:

fabricating a base package substrate having a component side and a system side;

coupling a first integrated circuit die on the component side;

coupling stacking interconnects on the component side around the first integrated circuit die;

forming a package body on the component side, the first integrated circuit die, and the stacking interconnects;

forming non-horizontal insertion cavities through the package body and on the stacking interconnects; and

forming a trench, in the package body, the trench continuously surrounding a central region of the package body and adjacent to the non-horizontal insertion cavities for reducing a package warping stress.

2. The method as claimed in claim 1 wherein forming the trench includes positioning the trench between the non-horizontal insertion cavities and the first integrated circuit die.

3. The method as claimed in claim 1 wherein forming the trench includes positioning the trench around the non-horizontal insertion cavities and the first integrated circuit die.

4. The method as claimed in claim 1 wherein forming the trench includes removing a portion of the package body to a level below a surface of the first integrated circuit die.

5. The method as claimed in claim 1 further comprising dividing an integrated circuit packaging system assembly strip having a notch.

6. A method of manufacture of an integrated circuit packaging system comprising:

fabricating a base package substrate having a component side and a system side including forming a component pad on the component side and a system pad on the system side;

coupling a first integrated circuit die on the component side including coupling a chip interconnect between the first integrated circuit die and the component pad;

coupling stacking interconnects on the component side around the first integrated circuit die;

forming a package body on the component side, the first integrated circuit die, and the stacking interconnects including injection molding an epoxy molding compound;

forming non-horizontal insertion cavities through the package body and on the stacking interconnects including exposing a top of the stacking interconnect; and

forming a trench, in the package body, the trench continuously surrounding a central region of the package body and adjacent to the non-horizontal insertion cavities for reducing a package warping stress including reducing a deformation height of the base package substrate.

7. The method as claimed in claim 6 wherein forming the trench includes positioning the trench between the non-horizontal insertion cavities and the first integrated circuit die including reducing a convex warped state of the base package substrate.

8. The method as claimed in claim 6 wherein forming the trench includes positioning the trench around the non-horizontal insertion cavities and the first integrated circuit die including reducing a concave warped state of the base package substrate.

9. The method as claimed in claim 6 wherein forming the trench includes removing a portion of the package body to a level below a surface of the first integrated circuit die including exposing a portion of the component side.

10. The method as claimed in claim 6 further comprising dividing an integrated circuit packaging system assembly strip having a notch.

11. An integrated circuit packaging system comprising:

a base package substrate having a component side and a system side;

a first integrated circuit die coupled on the component side;

stacking interconnects on the component side coupled around the first integrated circuit die;

a package body formed on the component side, the first integrated circuit die, and the stacking interconnects;

non-horizontal insertion cavities through the package body and on the stacking interconnects; and

a trench, in the package body, the trench continuously surrounding a central region of the package body and adjacent to the non-horizontal insertion cavities for reducing a deformation height.

12. The system as claimed in claim 11 wherein the trench, in the package body, includes the trench positioned between the non-horizontal insertion cavities and the first integrated circuit die.

13. The system as claimed in claim 11 wherein the trench, in the package body, includes the trench around the non-horizontal insertion cavities and the first integrated circuit die.

14. The system as claimed in claim 11 wherein the trench, in the package body, includes a portion of the package body removed to a level below a surface of the first integrated circuit die.

15. The system as claimed in claim 11 further comprising an adhesive material between the component side and the first integrated circuit die to enclose chip interconnects.

16. The system as claimed in claim 11 further comprising:

component pads on the component side and system pads on the system side;

chip interconnects between the first integrated circuit die and the component pads;

epoxy molding compound is the package body; and

a top of the stacking interconnect exposed by the non-horizontal insertion cavities.

17. The system as claimed in claim 16 wherein the trench, in the package body, includes the trench positioned between the non-horizontal insertion cavities and the first integrated circuit die for reducing a convex warped state of the base package substrate.

18. The system as claimed in claim 16 wherein the trench, in the package body, includes the trench around the non-horizontal insertion cavities and the first integrated circuit die for reducing a concave warped state of the base package substrate.

19. The system as claimed in claim 16 wherein the trench, in the package body, includes a portion of the package body removed to a level below a surface of the first integrated circuit die and a portion of the component side exposed in the trench.

20. The system as claimed in claim 16 further comprising system interconnects coupled to the system pads of the base package substrate.