Dummy wafers in 3DIC package assemblies

• US 8,378,480 B2
• Filed: 03/04/2010
• Issued: 02/19/2013
• Est. Priority Date: 03/04/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa, Lee, Chia-Yen
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US12/717,779
• Publication Number:
  US 20110215470A1
• Time in Patent Office: 1,083 Days
• Field of Search: None
• US Class Current: 257/704
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A package structure includes a first die, and a second die over and bonded to the first die. The second die has a size smaller than a size of the first die. A dummy chip is over and bonded onto the first die. The dummy chip includes a portion encircling the second die. The dummy chip includes a material selected from the group consisting essentially of silicon and a metal.

Claims

1. A package structure comprising:

a first die;

a second die over and bonded to the first die, wherein the second die has a size smaller than a size of the first die;

a dummy chip over the first die, wherein the dummy chip comprises a portion encircling the second die, wherein the dummy chip comprises a material selected from the group consisting essentially of silicon and a metal, wherein the dummy chip comprises an opening extending from a bottom surface to an intermediate level of the dummy chip, wherein a portion of the dummy chip covers the opening, and wherein the second die extends into the opening;

an adhesive adhering the dummy chip to the first die;

metal pillars extending from a top surface to a bottom surface of the dummy chip;

a gap in the opening and horizontally between a sidewall of the second die and a sidewall of the dummy chip; and

a thermally conductive material horizontally between and contacting the dummy chip and the second die, wherein the thermally conductive material is in physical contact with the sidewall of the second die and the sidewall of the dummy chip.

2. The package structure of claim 1, wherein the dummy chip is a dummy silicon chip.

3. The package structure of claim 1, wherein the first die is an interposer die substantially free from active devices.

4. The package structure of claim 3 further comprising a third die bonded to the interposer die, wherein the second die and the third die are on opposite sides of the interposer die.

5. The package structure of claim 4 further comprising solder bumps on a surface of the interposer die, wherein the solder bumps and the third die are on a same side of the interposer die.

6. The package structure of claim 4 further comprising a dummy silicon die bonded to the interposer die, wherein the dummy silicon die and the second die are on opposite sides of the interposer die, and wherein the dummy silicon die comprises an opening, with the third die being in the opening.

7. The package structure of claim 6 further comprising solder bumps on a side of the dummy silicon die and electrically connected to through-silicon vias in the dummy silicon die, wherein the interposer die and the solder bumps are on opposite sides of the dummy silicon die.

8. The package structure of claim 1, wherein the first die comprises active devices.

9. The package structure of claim 1, wherein the dummy chip is a dummy metal chip.

10. The package structure of claim 1, wherein the dummy chip comprises an opening extending from a top surface to a bottom surface of the dummy chip, with the second die extending into the opening.

11. The package structure of claim 1, wherein the thermally conductive material forms a ring encircling the second die.