Semiconductor apparatus including a metal alloy between a first contact and a second contact

• US 8,378,490 B2
• Filed: 03/15/2011
• Issued: 02/19/2013
• Est. Priority Date: 03/15/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ni, Chyi-Tsong, Wang, I-Shi, Lee, Hsin-Kuei, Su, Ching-Hou
• Primary Examiner(s): Pizarro, Marcos D.
• Assistant Examiner(s): Jahan, Bilkis
• Application Number:
  US13/048,127
• Publication Number:
  US 20120235301A1
• Time in Patent Office: 707 Days
• Field of Search: 257/757, 257/758, 257/210, 257/211, 257/503, 257/508
• US Class Current: 257/757
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/11826 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11827 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/11848 Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13562 On the entire exposed surface of the core
• CPC Class Codes: H01L 2224/13582 Two-layer coating
• CPC Class Codes: H01L 2224/13599 Material
• CPC Class Codes: H01L 2224/13624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13657 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/13666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/13684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/165 : Material
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/29599 : Material
• CPC Class Codes: H01L 2224/81011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/81097 : Heating
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/8121 : using a reflow oven
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/81948 : Thermal treatments, e.g. annealing, controlled cooling
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

A method of integrated circuit fabrication is provided, and more particularly fabrication of a semiconductor apparatus with a metallic alloy. An exemplary structure for a semiconductor apparatus comprises a first silicon substrate having a first contact comprising a silicide layer between the substrate and a first metal layer; a second silicon substrate having a second contact comprising a second metal layer; and a metallic alloy between the first metal layer of the first contact and the second metal layer of the second contact.

Claims

1. A semiconductor apparatus comprising:

a first silicon substrate having a first contact comprising a silicide layer between the substrate and a first metal layer, wherein a thickness ratio of the first metal layer to the silicide layer is from about 1 to 2;

a second silicon substrate having a second contact comprising a second metal layer; and

a metallic alloy between the first metal layer of the first contact and the second metal layer of the second contact.

2. The semiconductor apparatus of claim 1, wherein a width ratio of the first contact to the second contact is from about 0.12 to 1.2.

3. The semiconductor apparatus of claim 1, wherein the silicide layer comprises a material selected from a group of Ti, Co, Ni, W, and Pt.

4. The semiconductor apparatus of claim 1, wherein the first metal layer comprises a material selected from a group of Ti, Co, Ni, W, and Pt.

5. The semiconductor apparatus of claim 1, wherein the silicide layer is on the first metal layer.

6. The semiconductor apparatus of claim 1, wherein the silicide layer comprises a compound including silicon from the first silicon substrate and a material from the first metal layer.

7. The semiconductor apparatus of claim 1, wherein the second metal layer comprises Al or Al alloy.

8. The semiconductor apparatus of claim 1, wherein a thickness ratio of the second metal layer to the silicide layer is from about 12 to 25.

9. The semiconductor apparatus of claim 1, wherein the metallic alloy comprises an alloy of the first and second metal layers.

10. The semiconductor apparatus of claim 1, wherein the metallic alloy comprises a metallic compound.

11. The semiconductor apparatus of claim 10, wherein the metallic compound comprises Al.

12. The semiconductor apparatus of claim 1, wherein a thickness ratio of the metallic alloy to the silicide layer is from about 0.8 to 5.

13. The semiconductor apparatus of claim 1, wherein one of the first or second silicon substrates comprises a micro-electro-mechanical system (MEMS) device and the other substrate comprises an integrated circuit (IC) device.

14. The semiconductor apparatus of claim 1, wherein the first silicon substrate comprises a micro-electro-mechanical system (MEMS) device and the second silicon substrate comprises an integrated circuit (IC) device.

15. A semiconductor apparatus comprising:

a first silicon substrate;

a second silicon substrate;

a first contact structure between the first silicon substrate and the second silicon substrate;

a second contact structure between the first silicon substrate and the second silicon substrate, wherein each of the first and second contact structures comprise;

a first contact region comprising a silicide layer between the substrate and a first metal layer, wherein a thickness ratio of the first metal layer to the silicide layer is from about 1 to 2;

a second contact region comprising a second metal layer; and

a metallic alloy between the first metal layer of the first contact region and the second metal layer of the second contact region; and

a micro-electrical mechanical system (MEMS) device positioned between the first contact structure and the second contact structure.

16. The semiconductor apparatus of claim 15, wherein a thickness ratio of the metallic alloy to the silicide layer is from about 0.8 to 5.

17. The semiconductor apparatus of claim 15, wherein the first metal layer comprises a material selected from a group of Ti, Co, Ni, W, and Pt.

18. The semiconductor apparatus of claim 17, wherein the second metal layer comprises Al or Al alloy.

19. The semiconductor apparatus of claim 18, wherein the metallic alloy comprises an alloy of the first and second metal layers.

20. A semiconductor apparatus comprising:

a first silicon substrate having a first contact comprising a silicide layer between the substrate and a first metal layer;

a second silicon substrate having a second contact comprising a second metal layer, wherein a thickness ratio of the second metal layer to the silicide layer is from about 12 to 25; and

a metallic alloy between the first metal layer of the first contact and the second metal layer of the second contact.