Method for fabrication of a semiconductor device and structure

• US 8,378,494 B2
• Filed: 06/16/2011
• Issued: 02/19/2013
• Est. Priority Date: 04/14/2009
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Beinglass, Israel, de Jong, Jan Lodewijk
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US13/162,154
• Publication Number:
  US 20120032294A1
• Time in Patent Office: 614 Days
• Field of Search: 257/621, 257/797, 257/499, 257/773, 257/774, 257/E23.179, 438/458
• US Class Current: 257/773
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 27/11807 : CMOS gate arrays
• CPC Class Codes: H01L 27/11898 : Input and output buffer/driver structures
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices

Abstract

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

Claims

1. A semiconductor device comprising:

a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials;

a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors,

wherein alignment of said through via is based on said first alignment mark and said second alignment mark.

2. A semiconductor device according to claim 1, wherein said second layer comprises a single crystal silicon layer less than 0.4 micron thick.

3. A semiconductor device according to claim 1, wherein said second transistors are planar transistors.

4. A semiconductor device according to claim 1, wherein said second transistors comprises P type transistors and N type transistors.

5. A semiconductor device according to claim 1, wherein said second layer is transferred using an ion-cut process.

6. A semiconductor device according to claim 1, wherein said second layer comprises a repeating implant pattern.

7. A semiconductor device according to claim 1, wherein the location of said second transistors is defined by an etch process.

8. A semiconductor device comprising:

a first single crystal layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer,

a second layer overlying said first single crystal layer, said second layer comprising second transistors, second alignment mark, and a via forming part of a connection path between said first transistors and said second transistors,

wherein alignment of said via is effected by the distance between said first alignment mark and said second alignment mark.

9. A semiconductor device according to claim 8, wherein said second layer comprises a single crystal silicon layer less than 0.4 micron thick.

10. A semiconductor device according to claim 8, wherein said second transistors are planar transistors.

11. A semiconductor device according to claim 8, wherein said second transistors comprises P type transistors and N type transistors.

12. A semiconductor device according to claim 8, wherein said second layer is transferred using an ion-cut process.

13. A semiconductor device according to claim 8, wherein said second layer comprises a repeating implant pattern.

14. A semiconductor device according to claim 8, wherein said second transistors are recessed channel transistors or junction-less transistors.

15. A semiconductor device comprising:

a first single crystal layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal layer, wherein said at least one metal layer comprises copper or aluminum;

a second mono-crystallized layer overlying said at least one metal layer; and

said second mono-crystallized layer comprises second transistors wherein said second transistors comprise P type transistors and N type transistors, and wherein

said second transistors are aligned to said first alignment mark with less than 100 nm alignment error.

16. A semiconductor device according to claim 15, wherein said second transistors are horizontal oriented transistors.

17. A semiconductor device according to claim 15,

wherein said second mono-crystallized layer comprises second alignment mark, and a through via through said second mono-crystallized layer, wherein said through via is a part of a connection path between said first transistors and said second transistors,

wherein alignment of said through via is effected by the distance between said first alignment mark and said second alignment mark.

18. A semiconductor device according to claim 15, wherein said second layer comprises a repeating implant pattern.

19. A semiconductor device according to claim 15, wherein said second transistors are recessed channel transistors or junction-less transistors.

20. A semiconductor device according to claim 15, wherein the location of said second transistors defined by an etch process.

21. A semiconductor device according to claim 15, wherein said second mono-crystallized layer is less than 0.4 micron thick.