5V tolerant circuit for CML transceiver in AC-couple

• US 8,378,714 B2
• Filed: 07/01/2010
• Issued: 02/19/2013
• Est. Priority Date: 07/01/2010
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Kai, Lei, Han, Bi, Liang, Xu
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US12/829,087
• Publication Number:
  US 20120001671A1
• Time in Patent Office: 964 Days
• Field of Search: 326 80- 83, 326 86- 87, 326112-113, 326/115, 327108-109, 327/112, 327/333
• US Class Current: 326/83
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03F 2203/45101 Control of the DC level being present
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/45632 in differential amplifiers with FET transistors as the active amplifying circuit H03F3/4578 takes precedence

Abstract

A high voltage tolerant transceiver operating at a low voltage is provided, including two input/output pads to receive a receive signal and transmit a transmit signal; a transmitter block to transmit the transmit signal; a receiver block to receive the receive signal and provide an amplified signal; at least one of the transmitter block and the receiver block further comprising at least two NMOS transistors having their gate coupled to a low power supply to receive the low voltage, their substrate coupled to ground, and their source coupled to the input/output pad. Also provided is a circuit to isolate the output of a transmitter from high voltages, including a first transistor and a second transistor. Also provided is a substrate isolating circuit, including a first transistor, a second transistor, and a third transistor so that the substrate voltage is isolated from a high voltage in the pads. Further provided is a bias isolating circuit so that an input bias voltage is isolated from a high voltage in the pads.

Claims

1. A high voltage tolerant transceiver operating at a low voltage, the transceiver comprising:

at least two input/output pads to receive a receive signal and transmit a transmit signal;

a transmitter block to transmit the transmit signal;

a receiver block to receive the receive signal and provide an amplified signal;

at least one of the transmitter block and the receiver block further comprising at least two NMOS transistors having their gate coupled to a low power supply to receive the low voltage, their substrate coupled to ground, and their source coupled to the input/output pad.

2. The high voltage tolerant transceiver of claim 1 further comprising

a common mode bias block to adjust the common mode voltage across the at least two input/output pads;

a resistor block coupled to the common mode bias block to provide the common mode voltage to the input/output pads of the transceiver circuit;

the common mode bias block further comprising

a substrate isolating circuit, and a bias isolating circuit.

3. The high voltage tolerant transceiver of claim 1 wherein the high voltage is 5V and the low voltage is 2.5 V.

4. The high voltage tolerant transceiver of claim 1 wherein the transceiver is an AC-coupled, CML transceiver.

5. A circuit to isolate the output of a transmitter from high voltages comprising:

a first transistor with substrate coupled to ground, gate coupled to a low voltage, source coupled to a positive output pad, and drain coupled to an output of the transmitter device; and

a second transistor with substrate coupled to ground, gate coupled to a low voltage, source coupled to a negative output pad, and drain coupled to an output of the transmitter device.

6. The circuit of claim 5 wherein the high voltages are voltages between 2.5 V and 5 V.

7. A substrate isolating circuit, comprising:

a first transistor with gate coupled through a resistor to ground and source coupled to a low voltage;

a second transistor with gate coupled to the low voltage, source coupled to the drain of the first transistor, and drain coupled to a pad; and

a third transistor with gate coupled to the low voltage, source coupled to the gate of the first transistor, and drain coupled to the pad;

wherein a substrate voltage is supplied by the drain of the first transistor, and the substrate voltage is isolated from a high voltage in the pad.

8. The circuit of claim 7 wherein the high voltages are voltages between 2.5 V and 5 V and the low voltage is 2.5 V.

9. A bias isolating circuit comprising:

a first transistor with gate coupled to a low voltage, source coupled through a resistor to ground and drain coupled to a pad;

a second transistor with gate coupled through the resistor to ground, drain coupled to an input bias voltage, and substrate coupled to the low voltage;

a third transistor with gate coupled through the resistor to ground, drain coupled to the low voltage, and substrate coupled to ground;

wherein a bias voltage is supplied by the sources of the second and third transistors coupled together, and the input bias voltage is isolated from a high voltage in the pad.

10. The circuit of claim 9 wherein the high voltages are voltages between 2.5 V and 5V and the low voltage is 2.5V.