Method to construct systems

• US 8,378,715 B2
• Filed: 08/24/2012
• Issued: 02/19/2013
• Est. Priority Date: 04/14/2009
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Ze'ev
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US13/593,620
• Publication Number:
  US 20120322203A1
• Time in Patent Office: 179 Days
• Field of Search: None
• US Class Current: 326/101
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1435 : Random access memory [RAM]
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/37001 : Yield

Abstract

A method to construct first and second configurable systems including: providing a first configurable system including a first die and a second die, where the first die is diced from a first wafer and the second die is diced from a second wafer and the first die is connected to the second die using at least one through-silicon-via (TSV); providing a second configurable system including a third die and a fourth die, where the third die is diced from a third wafer and the fourth die is diced from a fourth wafer and the third die is connected to the fourth die using at least one through-silicon-via (TSV); where processing the first wafer and the third wafer utilizes a majority of masks that are substantially same; and where the first die is larger than the third die.

Claims

1. A method to construct first and second configurable systems comprising:

providing a first configurable system comprising a first die and a second die, wherein said first die is diced from a first wafer and said second die is diced from a second wafer and said first die is connected to said second die using at least one through-silicon-via (TSV);

providing a second configurable system comprising a third die and a fourth die, wherein said third die is diced from a third wafer and said fourth die is diced from a fourth wafer and said third die is connected to said fourth die using at least one through-silicon-via (TSV);

wherein processing said first wafer and said third wafer utilizes a majority of masks that are substantially same;

and wherein said first die is larger than said third die.

2. The method to construct first and second configurable systems according to claim 1, wherein said first die is a field programmable gate array (FPGA) die.

3. The method to construct first and second configurable systems according to claim 1, wherein said second die comprises a configurable I/O die for the connection of said first configurable system to external devices.

4. The method to construct first and second configurable systems according to claim 1, wherein said second die comprises a configurable memory.

5. The method to construct first and second configurable systems according to claim 1, wherein said first die comprises a repeating array of functional units, and each of said functional units comprises a microcontroller unit (MCU) and at least one of said micro controller units is used for at least a portion of the first configurable system set-up.

6. The method to construct first and second configurable systems according to claim 1, wherein said diced from a first wafer comprises an etch step to define dice lines.

7. The method to construct first and second configurable systems according to claim 1, wherein said first die comprises at least one unused potential dice line.

8. A method to construct first and second configurable systems comprising:

providing a first configurable system comprising a first die and a second die, wherein said first die is diced from a first wafer and said second die is diced from a second wafer and said first die is connected to said second die using at least one through-silicon-via (TSV);

providing a second configurable system comprising a third die and a fourth die, wherein said third die is diced from a third wafer and said fourth die is diced from a fourth wafer and said third die is connected to said fourth die using at least one through-silicon-via (TSV);

wherein said second die and said fourth die are adapted to connect the said configurable systems to at least one external device, and

said second die is larger than said fourth die, and

processing said second wafer and said fourth wafer utilizes a majority of masks that are substantially same.

9. The method to construct first and second configurable systems according to claim 8, wherein said first die is a field programmable gate array (FPGA) die.

10. The method to construct first and second configurable systems according to claim 8, wherein said first die comprises a repeating array of functional units, and each of said functional units comprises a microcontroller unit (MCU) and at least one of said micro controller unit is used for at least a portion of the first configurable system set-up.

11. The method to construct first and second configurable systems according to claim 8, wherein said diced from a second wafer comprises an etch step to define dice lines.

12. The method to construct first and second configurable systems according to claim 8, wherein said second die comprises at least one unused potential dice line.

13. The method to construct first and second configurable systems according to claim 8, wherein said first die comprises a configurable memory.

14. A method to construct first and second systems comprising:

providing a first system comprising a first die and a second die, wherein said first die is diced from a first wafer and said second die is diced from a second wafer and said first die is connected to said second die using at least one through-silicon-via (TSV);

providing a second system comprising a third die and a fourth die, wherein said third die is diced from a third wafer and said fourth die is diced from a fourth wafer and said third die is connected to said fourth die using at least one through-silicon-via (TSV);

wherein said first die is larger than said third die, and

processing said first wafer and said third wafer utilizes a majority of masks that are substantially same.

15. The method to construct first and second systems according to claim 14, wherein said first die is a field programmable gate array (FPGA) die.

16. The method to construct first and second systems according to claim 14, wherein said second die comprises an I/O die for the connection of said first system to external devices.

17. The method to construct first and second systems according to claim 14, wherein said first die comprises configurable memory.

18. The method to construct first and second systems according to claim 14, wherein said first die comprises a repeating array of functional units, and each of said functional units comprises a microcontroller unit (MCU) and at least one of said micro controller units is used for at least a portion of the first system set-up.

19. The method to construct first and second systems according to claim 14, wherein said diced from a first wafer comprises an etch step to define dice lines.

20. The method to construct first and second systems according to claim 14, wherein said first die comprises at least one potential dice line.