Memory with interleaved read and redundant columns

• US 8,379,448 B2
• Filed: 11/30/2011
• Issued: 02/19/2013
• Est. Priority Date: 07/23/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Han, Jin-Man, Yip, Aaron
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US13/308,405
• Publication Number:
  US 20120069659A1
• Time in Patent Office: 447 Days
• Field of Search: 365/185.09, 365/185.11, 365/189.02, 365/189.05, 365/200, 365/230.03, 365/230.04
• US Class Current: 365/185.09
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: G11C 29/846 by choosing redundant lines at an output stage

Abstract

Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.

Claims

1. A memory device comprising:

a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells electrically coupled to the bit line, the plurality of columns comprising;

a plurality of regular interleave groups of regular columns; and

a plurality of redundant interleave groups of redundant columns, wherein each of the plurality of redundant interleave groups is associated with a corresponding regular group of the plurality of regular interleave groups;

wherein the memory device is configured to perform an n-way interleaved read scheme when the number of defective regular columns in each of the regular interleave groups is not greater than the number of redundant columns in its corresponding redundant interleave group, wherein n equals the number of regular interleaved groups, and

wherein the memory device is configured to perform an m-way interleaved read scheme when the number of defective regular columns in any of the regular interleave groups is greater than the number of redundant columns in its corresponding redundant interleave group, wherein m is less than the number of regular interleaved groups.

2. The memory device of claim 1, wherein the memory device is configured to switch among one-way, two-way, and four-way interleaved read schemes.

3. The memory device of claim 1, wherein the memory device is a NAND flash memory device.

4. The memory device of claim 1, wherein each of the memory cells comprise a floating gate transistor.

5. An apparatus comprising:

a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells electrically coupled to the bit line, the plurality of columns comprising;

a plurality of regular interleave groups of regular columns; and

a plurality of redundant interleave groups of redundant columns, wherein each of the plurality of redundant interleave groups is associated with a corresponding regular group of the plurality of regular interleave groups;

wherein the apparatus is configured to store data associated with a defective regular column of a first regular interleave group of the plurality of regular interleave groups in a redundant column of a redundant interleave group corresponding to a different regular interleave group of the plurality of redundant interleave groups when there are more defective columns in the first regular interleave group than redundant columns in the corresponding redundant interleave group, and

wherein the apparatus is configured to perform an interleave read scheme from the memory block.

6. The apparatus of claim 5, wherein the apparatus is configured to store data associated with a different defective regular column of the first regular interleave group in a redundant column of the corresponding redundant interleave group when there are not more defective columns in the first regular interleave group than redundant columns in the corresponding redundant interleave group.

7. The apparatus of claim 5, wherein the apparatus is configured to switch among two or more of one-way, two-way, or four-way interleaved read schemes.

8. The apparatus of claim 5, wherein the plurality of regular interleave groups comprise at least one regular odd group and at least one regular even group, and wherein the plurality of redundant interleave groups comprise at least one redundant odd group and at least one redundant even group.

9. The apparatus of claim 8, wherein the regular odd group comprises the defective column and the redundant even group comprises the redundant column.

10. The apparatus of claim 5, wherein the memory block is embodied in a NAND flash memory.

11. An apparatus comprising:

a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells electrically coupled to the bit line, the plurality of columns comprising;

a plurality of regular interleave groups of regular columns, wherein the plurality of regular interleave groups comprise a first regular interleave group, a second regular interleave group, a third regular interleave group, and a fourth regular interleave group; and

a plurality of redundant interleave groups of redundant columns, wherein each of the plurality of redundant interleave groups is associated with a corresponding regular group of the plurality of regular interleave groups;

wherein the apparatus is configured to store data associated with a defective regular column of the first regular interleave group of the plurality of regular interleave groups in a redundant column of a redundant interleave group corresponding to a different regular interleave group of the plurality of redundant interleave groups, wherein the redundant interleave group corresponding to the different regular interleave group is one of a second redundant interleave group corresponding to the second regular interleave group, a third redundant interleave group corresponding to the third regular interleave group, or a fourth redundant regular interleave group corresponding to the fourth regular interleave group, and

wherein the apparatus is configured to perform an interleave read scheme from the memory block.

12. The apparatus of claim 11, wherein the apparatus is configured to store data associated with the defective regular column of the first regular interleave group in the redundant column of the redundant interleave group corresponding to the different regular interleave group when there are more defective columns in the first regular interleave group than redundant columns in the corresponding redundant interleave group.

13. The apparatus of claim 12, wherein the apparatus is configured to store data associated with a different defective regular column of the first regular interleave group in a redundant column of the corresponding redundant interleave group when there are not more defective columns in the first regular interleave group than redundant columns in the corresponding redundant interleave group.

14. The apparatus of claim 11, wherein the apparatus is configured to switch among two-way and four-way interleaved read schemes.

15. The apparatus of claim 11, where in the memory block is embodied in a NAND flash memory.

16. An apparatus comprising:

a memory block having a plurality of columns, each of the columns comprising a bit line and a plurality of memory cells electrically coupled to the bit line, the plurality of columns comprising a first regular interleave group of regular columns, a second regular interleave group of regular columns, a first redundant interleave group of redundant columns associated with the first regular interleave group, and a second redundant interleave group of redundant columns associated with the second regular interleave group; and

a multiplexer configured to;

receive data corresponding to the first regular interleave group, the second regular interleave group, the first redundant interleave group, and the second redundant interleave group; and

sequentially output data associated with addresses of regular columns of the first regular interleave group and data associated with addresses of regular columns of the second interleave group in an alternating manner to perform an interleaved read scheme,

wherein the multiplexer is configured to output data stored at an address of a redundant column in the first redundant interleave group in place of data at an address of a defective regular column in the first regular interleave group, and

wherein the multiplexer is configured to output data stored at an address of a redundant column in the second redundant interleave group in place of the data at an address of the different defective regular column in the first regular interleave group.

17. The apparatus of claim 16, further comprising a redundancy selector configured to:

map the address of defective regular column of the first regular interleave group to the address of a redundant column of the first redundant interleave group; and

map the address of a different defective regular column of the first regular interleave group to the address of the redundant column of the second redundant interleave group.

18. The apparatus of claim 17, wherein the redundancy selector is configured to assert a redundant hit signal in response to receiving address data associated with at least one of the defective regular column or the different defective regular column.

19. The apparatus of claim 18, wherein the multiplexer is configured to output data stored at the address of the redundant column of the first regular interleave group in place of data at the address of the defective regular column based at least in part on the redundant hit signal, and wherein the multiplexer is configured to output data stored at the address of the redundant column in the second redundant interleave group in place of the data at an address of the different defective regular column based at least in part on the redundant hit signal.

20. The apparatus of claim 16, further comprising an interleave group selector configured to generate at least one control signal indicative of whether to output data corresponding to the first regular interleave group, the second regular interleave group, the first redundant interleave group, or the second redundant interleave group from the multiplexer, and to provide the at least one control signal to the multiplexer.