Detection of broken word-lines in memory arrays

• US 8,379,454 B2
• Filed: 05/05/2011
• Issued: 02/19/2013
• Est. Priority Date: 05/05/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Kochar, Mrinal, Huang, Jianmin, Wan, Jun
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/101,765
• Publication Number:
  US 20120281479A1
• Time in Patent Office: 656 Days
• Field of Search: 365/185.19, 365/185.29, 365/189.011, 365/218
• US Class Current: 365/185.19
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. An “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. The number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n−1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.

Claims

1. A method of operating a non-volatile memory circuit having an array including a plurality of erase blocks each including a plurality of memory cells formed along word-lines, comprising:

determining whether a word-line is defective by a process including;

performing first write operation on a first plurality of memory cells along a first word-line from a first erase block, the first write operation including a series of alternating programming pulses and verify operations, the first plurality of memory cells along the first word-line individually locking out from further programming pulses as verified;

determining the number of programming pulses in the first write operation for the memory cells of the first plurality of memory cells along the first word-line to verify as written;

subsequently performing a second write operation on a first plurality of memory cells along a second word-line from the first erase block, the second write operation including a series of alternating programming pulses and verify operations, the first plurality of memory cells along the second word-line individually locking out from further programming pulses as verified;

determining the number of programming pulses in the second write operation for the memory cells of the first plurality of memory cells along the second word-line to verify as written;

determining whether the number of programming pulses in the second write operation relative to the number of programming pulses in the first write operation exceeds a threshold value; and

in response to the number of programming pulses in the second write operation relative to the number of programming pulses in the first write operation exceeding the threshold, determining that the second word-line is defective.

2. The method of claim 1, further comprising:

subsequently setting a status indicator in a data management structure for the memory circuit to indicate that the first erase block is defective.

3. The method of claim 1, further comprising:

subsequently transferring the data written in the first write operation and any data previously written into the first erase block to another erase block.

4. The method of claim 1, wherein the non-volatile memory circuit is part of a memory system including a controller circuit connected thereto and wherein the determining whether the number of programming pulses in the second write operation relative to the number of programming pulses in the first write operation exceeds a threshold value and the determining that the second word-line is defective are performed by logic circuitry on the controller circuit.

5. The method of claim 1, wherein the non-volatile memory circuit includes a state machine and wherein the determining whether the number of programming pulses in the second write operation relative to the number of programming pulses in the first write operation exceeds a threshold value and the determining that the second word-line is defective are performed by logic circuitry on the state machine.

6. The method of claim 1, wherein the threshold is a settable parameter.

7. The method of claim 1, further comprising:

prior to determining whether the number of programming pulses in the second write operation relative to the number of programming pulses in the first write operation exceeds a threshold value, determining that the first word-line is not defective.

8. The method of claim 1, wherein the second word-line is a word-line adjacent to the first word-line.

9. The method of claim 1, wherein there is an intervening word-line between the second word-line and the first word-line.

10. The method of claim 1, wherein the first plurality of memory cells along first word-line are all of the cells connected along the first world-line and the first plurality of memory cells along second word-line are all of the cells connected along the second world-line.

11. The method of claim 1, wherein said determining process is performed for all word-lines of the first block except for the initial one or more adjacent word-lines and for the final one or more adjacent word-lines.