Semiconductor device and structure

• US 8,379,458 B1
• Filed: 10/13/2010
• Issued: 02/19/2013
• Est. Priority Date: 10/13/2010
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Widjaja, Yuniarto, Sekar, Deepak C.
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US12/904,124
• Time in Patent Office: 860 Days
• Field of Search: 365/185.03, 365/185.18, 365/185.19, 365/185.25, 365/185.26, 365/185.011, 365/175, 365/177
• US Class Current: 365/189.011
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/788 : with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/18 : Peripheral circuit regions
• CPC Class Codes: H10B 12/053 : the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 : the transistor being a FinFET
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/41 : of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

A method of performing a holding operation to a semiconductor memory array having rows and columns of memory cells by applying an electrical signal to collector regions of multiplicity of said memory cells in parallel, wherein said collector region of said memory cells in a row of said memory array is connected to a common control line, wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein at least one of said memory cells further comprises another memory cell on top thereof; and wherein said holding operation maintains charges stored in said floating body region of multiplicity of memory cells connected to said common control line.

Claims

1. A method of performing a holding operation to a semiconductor memory array having rows and columns of memory cells, the method comprising:

applying an electrical signal to collector regions of multiplicity of said memory cells in parallel,

wherein said collector region of said memory cells in a row of said memory array is connected to a common control line,

wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and

wherein at least one of said memory cells further comprises another memory cell on top thereof; and

wherein said holding operation maintains charges stored in said floating body region of multiplicity of memory cells connected to said common control line.

2. The method of claim 1, wherein said another memory cell comprises mono crystal.

3. The method of claim 1, wherein each of said memory cells formation comprises layer transfer operations.

4. The method of claim 1, wherein each of said memory cells further comprises a gate region at their side and is insulated therefrom by an insulating layer.

5. The method of claim 1, wherein said electrical signal applied to said collector region comprises a pulse.

6. The method of claim 1, wherein said electrical signal applied to said collector region comprises a constant amplitude level.

7. The method of claim 2, wherein the formation of said memory cell and said similar memory cell comprises at least one process operation performed in parallel.

8. A semiconductor memory array having rows and columns of memory cells, comprising:

a common control line coupled to collector regions of a multiplicity of said memory cells to provide an electrical signal in parallel,

wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;

wherein each of said memory cells further comprises another memory cell on top thereof; and

wherein a holding operation may be performed to maintain charges stored in said floating body region of multiplicity of memory cells connected to said common control line.

9. The memory array of claim 8, wherein said another memory cell comprises mono crystal.

10. The method of claim 8, wherein each of said memory cells formation comprises layer transfer operations.

11. The memory array of claim 8, wherein each of said memory cells further comprises a gate region at a side and is insulated therefrom by an insulating layer.

12. The memory array of claim 8, wherein said electrical signal applied to said collector region comprises a pulse.

13. The memory array of claim 8, wherein said electrical signal applied to said collector region comprises a constant amplitude level.

14. The memory array of claim 9, wherein the formation of said memory cell and said similar memory cell comprise at least one process operation performed in parallel.

15. A method of operating a semiconductor memory array having rows and columns of memory cells, wherein each memory cell has a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;

a second region having a second conductivity type; and

a third region defining at least a further portion of the memory cell, the third region having the second conductivity type, the method comprising;

applying in parallel electrical signals to the third region of memory cell of said semiconductor memory array; and

flowing a current into the second region of the memory cell to maintain charges stored in said floating body; and

wherein each of said memory cells further comprises another memory cell on top thereof.

16. The method of claim 15, wherein said another memory cell comprises mono crystal.

17. The method of claim 15, wherein each of said memory cells formation comprises layer transfer operations.

18. The method of claim 15, wherein said electrical signal applied to said third region comprises a pulse.

19. The method of claim 15, wherein said electrical signal applied to said third region comprises a constant amplitude level.

20. The method of claim 16, wherein the formation of said memory cell and said similar memory cell comprise at least one process operation performed in parallel.

21. The method of claim 15, wherein said electrical signals applied to said third region are of different amplitude or polarity, depending on an operation of said memory cell.

22. The method of claim 15, further comprising:

reading a state of the memory cell via said current flowing from said third region to said second region.

23. The method of claim 15, wherein said current has an amplitude that is different when said memory cell is in a first data state than when said memory cell is in a second data state.

24. The method of claim 15, further comprising:

writing a first data state to said memory cell by injecting a charge to said floating body region via said current flowing from said third region into said second region.

25. The method of claim 15, further comprising:

applying the electrical signals of different amplitude or polarity to said third region depending on an operation of said memory cell.

26. A method of performing a holding operation to a semiconductor memory array having rows and columns of memory cells, the method comprising:

applying an electrical signal to collector regions of multiplicity of said memory cells in parallel,

wherein said collector region of said memory cells in a column of said memory array is connected to a common control line,

wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and

wherein each of said memory cells further comprises another memory cell on top thereof; and

wherein said holding operation maintains charges to multiplicity of memory cells connected to said common line.

27. The method of claim 26, wherein said another memory cell comprises mono crystal.

28. The method of claim 26, wherein each of said memory cells formation comprises layer transfer operations.

29. The method of claim 26, wherein each of said memory cells further comprises a gate region at their side and is insulated therefrom by an insulating layer.

30. The method of claim 26, wherein said electrical signal applied to said collector region comprises a pulse.

31. The method of claim 26, wherein said electrical signal applied to said collector region comprises a constant amplitude level.

32. The method of claim 27, wherein the formation of said memory cell and said similar memory cell comprises at least one process operation performed in parallel.