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Semiconductor device and structure

  • US 8,379,458 B1
  • Filed: 10/13/2010
  • Issued: 02/19/2013
  • Est. Priority Date: 10/13/2010
  • Status: Active Grant
First Claim
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1. A method of performing a holding operation to a semiconductor memory array having rows and columns of memory cells, the method comprising:

  • applying an electrical signal to collector regions of multiplicity of said memory cells in parallel,wherein said collector region of said memory cells in a row of said memory array is connected to a common control line,wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and

    wherein at least one of said memory cells further comprises another memory cell on top thereof; and

    wherein said holding operation maintains charges stored in said floating body region of multiplicity of memory cells connected to said common control line.

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