Wide-band signal processor

• US 8,379,740 B2
• Filed: 12/21/2009
• Issued: 02/19/2013
• Est. Priority Date: 12/23/2008
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Menu, Michel, Bourmeyster, Ivan
• Primary Examiner(s): Vo, Don N
• Application Number:
  US12/643,489
• Publication Number:
  US 20100158158A1
• Time in Patent Office: 1,156 Days
• Field of Search: 375/260, 375/295
• US Class Current: 375/260
• CPC Class Codes: G10L 19/0204 using subband decomposition
• CPC Class Codes: H03H 17/0266 Filter banks

Abstract

A signal processor for processing a digital input signal including samples sampled at a sampling frequency, the signal processor comprising a plurality of filters arranged to divide the digital input signal into a first signal in a first frequency band below a first cut-off frequency, and a second signal in a second frequency band above a second cut-off frequency; first frequency shifting circuitry arranged to shift the second signal to a frequency band below the first cut-off frequency; decimation circuitry arranged to decimate the first signal and the shifted second signal; and processing circuitry arranged to process the decimated first and second signals.

Claims

1. A signal processor for processing a digital input signal comprising samples sampled at a sampling frequency, the signal processor comprising:

a plurality of filters arranged to divide the digital input signal into a first signal in a first frequency band below a first cut-off frequency, and a second signal in a second frequency band above a second cut-off frequency;

first frequency shifting circuitry arranged to shift the second signal to a frequency band below the first cut-off frequency;

decimation circuitry arranged to decimate the first signal to generate a first decimated signal and the second frequency shifted signal to generate a second decimated signal, the first and second decimated signals having samples at most at half the sampling frequency of the digital input signal, wherein the decimation circuitry is arranged to receive the second frequency shifted signal from the first frequency shifting circuitry; and

processing circuitry arranged to process the decimated first and second signals.

2. The signal processor of claim 1, wherein the first frequency shifting circuitry comprises:

first modulating circuitry arranged to modulate the second signal by a modulating signal at a modulation frequency; and

a low-pass filter arranged to filter the modulated signal.

3. The signal processor of claim 2, wherein the first cut-off frequency is equal to f_s/4−

d_f1, wherein f_s is the sampling frequency, and d_f1 is a first frequency spacing, and the second cut-off frequency is equal to f_s/4−

d_f2, where d_f2 is a second frequency spacing.

4. The signal processor of claim 3, wherein d_f1 and d_f2 are each equal to between 20 Hz and 1 kHz.

5. The signal processor of claim 3, wherein digital input signal has a frequency band between 0 Hz and a high frequency limit fh, the second signal has a frequency band between the second cut-off frequency and a third cut-off frequency equal to f_h/2+d_f3, wherein d_f3 is a third frequency spacing equal to between 20 Hz and 1 kHz.

6. The signal processor of claim 5, further comprising:

insertion circuitry coupled to first and second outputs of the processing circuitry for receiving the first and second processed signals respectively, and arranged to insert samples into the processed first and second signals to generate modified first and second signals;

second frequency shifting circuitry arranged to shift the second modified signal to a frequency band above the second cut-off frequency; and

signal reconstruction circuitry arranged to combine said first modified signal and the frequency shifted second modified signal to generate an output signal having samples at said sampling frequency.

7. The signal processor of claim 6, wherein the second frequency shifting circuitry comprises:

second modulation circuitry arranged to modulate the second signal by said modulating signal at the modulation frequency; and

a high-pass filter arranged to filter the output of the second modulation circuitry.

8. The signal processor of claim 6, wherein the first and second frequency shifting circuitry each further comprise an amplifier for amplifying the modulated signals.

9. The signal processor of claim 7, wherein the high-pass filter has a cut-off frequency equal to the second cut-off frequency minus a fourth frequency spacing d_f4 equal to between 20 Hz and 1 kHz.

10. The signal processor of claim 9, wherein the first, second, third and fourth frequency spacings are chosen such that:

f_mod>

f_h−

f_s/4+d_f1+d_f3

f_mod<

f_s/4−

d_f1−

d_f2−

d_f4/2,

wherein f_mod is the modulation frequency, f_h is the high frequency limit of the input digital signal, f_s is the sampling frequency of the input digital signal, and d_f1 to d_f4 are the first, second, third and fourth frequency spacings respectively.

11. The signal processor of claim 10, further comprising a delay element coupled between the first output of the processing circuitry and the insertion circuitry.

12. The signal processor of claim 11, wherein the processing circuitry is arranged to remove acoustic echoes from said digital input signal.

13. A communications device comprising a speaker, a microphone, and the signal processor of claim 12.

14. A method of processing a digital input signal comprising samples sampled at a sampling frequency, the method comprising:

dividing, by a plurality of filters, the digital input signal into a first signal in a first frequency band below a first cut-off frequency, and a second signal in a second frequency band above a second cut-off frequency;

shifting by first frequency shifting circuitry the second signal to a frequency band below the first cut-off frequency;

performing decimation by decimation circuitry on the first signal to generate a first decimated signal and on the second frequency shifted signal to generate a second decimated signal, the first and second decimated signals having samples at most at half the sampling frequency of the digital input signal, wherein decimation of the second frequency shifted signal follows shifting of the second signal to a frequency band below the first cut-off frequency; and

processing, by processing circuitry, the decimated first and second signals.

15. The method of claim 14, further comprising:

inserting samples into the processed first and second signals to generate modified first and second signals;

shifting the second modified signal to a frequency band above the second cut-off frequency; and

combining the first modified signal and the frequency shifted second modified signal to generate an output signal having samples at the sampling frequency.

16. A signal processor comprising:

a first filter configured to select from a digital input signal a first signal in a first frequency band below a first cut-off frequency;

a second filter configured to select from the digital input signal a second signal in a second frequency band above a second cut-off frequency;

a first frequency shifting circuit configured to shift the second signal to a frequency band below the first cut-off frequency;

a first decimation circuit configured to decimate the first signal to generate a first decimated signal;

a second decimation circuit configured to receive the frequency shifted second signal from the first frequency shifting circuit and to decimate the frequency shifted second signal to generate a second decimated signal, the first and second decimated signals having samples at most at half a sampling frequency of the digital input signal; and

a processing circuit configured to process the first and second decimated signals.

17. A signal processor as defined in claim 16, wherein the first frequency shifting circuit comprises:

a first modulating circuit configured to modulate the second signal by a modulating signal at a modulation frequency; and

a low pass filter configured to filter the modulated signal.

18. A signal processor as defined in claim 17, wherein the first cut-off frequency is equal to f_s/4−

d_f1, where f_s is the sampling frequency and d_f1 is a first frequency spacing, and the second cut-off frequency is equal to f_s/4−

d_f2, where d_f2 is a second frequency spacing.

19. A signal processor as defined in claim 18, wherein the digital input signal has a frequency band between 0 Hz and a high frequency limit fh, the second signal has a frequency band between the second cut-off frequency and a third cut-off frequency equal to f_h/2+d_f3, wherein d_f3 is a third frequency spacing equal to between 20 Hz and 1 kHz.

20. A signal processor as defined in claim 17, further comprising:

first and second insertion circuits coupled to first and second outputs of the processing circuit, respectively, and configured to receive first and second processed signals from the processing circuit and to insert samples into the first and second processed signals to generate first and second modified signals, respectively;

a second frequency shifting circuit configured to shift the second modified signal to a frequency band above the second cut-off frequency; and

a signal reconstruction circuit configured to combine the first modified signal and the frequency shifted second modified signal to generate an output signal having samples at the sampling frequency.

21. A signal processor as defined in claim 20, wherein the second frequency shifting circuit comprises:

a second modulation circuit configured to modulate the second modified signal by the modulating signal at the modulation frequency; and

a high pass filter configured to filter an output of the second modulation circuit.

22. A signal processor as defined in claim 20, wherein the first and second frequency shifting circuits each further comprise an amplifier configured to amplify the respective frequency shifted signals.

23. A method for signal processing comprising:

selecting from a digital input signal a first signal in a first frequency band below a first cut-off frequency;

selecting from the digital input signal a second signal in a second frequency band above a second cut-off frequency;

frequency shifting the second signal to a frequency band below the first cut-off frequency;

decimating the first signal to generate a first decimated signal;

decimating the frequency shifted second signal to generate a second decimated signal, the first and second decimated signals having samples at most at half a sampling frequency of the digital input signal; and

processing the first and second decimated signals.

24. A method as defined in claim 23, wherein frequency shifting the second signal comprises:

modulating the second signal by a modulating signal at a modulation frequency; and

low pass filtering the modulated signal.

25. A method as defined in claim 24, further comprising:

receiving first and second processed signals and inserting samples into the first and second processed signals to generate first and second modified signals, respectively;

shifting the second modified signal to a frequency band above the second cut-off frequency; and

combining the first modified signal and the frequency shifted second modified signal to generate an output signal having samples at the sampling frequency.

26. A method as defined in claim 25, wherein shifting the second modified signal comprises:

modulating the second modified signal by the modulation signal at the modulation frequency; and

high pass filtering the modulated second modified signal.

27. A signal processor as defined in claim 25, further comprising amplifying the first frequency shifted second signal and the frequency shifted second modified signal.