Adaptable datapath for a digital processing system
First Claim
1. A reconfigurable data path circuit coupled to a memory bus for obtaining data from a memory, the reconfigurable data path circuit comprising:
- a plurality of functional units configured to perform a digital operation;
one or more data address generators coupled to the memory bus;
a configurable data path configurably coupled to the one or more data address generators and the plurality of functional units, the configurable data path being configurable in response to a first configuration information by configuring or reconfiguring at least one interconnection between the one or more data address generators and the plurality of functional units;
wherein the one or more data address generators are coupled to the memory bus and the configurable data path, each of the one or more data address generators being configurable in response to a second configuration information that is different from the first configuration information to generate memory addresses from which data is to be read from or written to the memory for the data path configuration; and
wherein the second configuration information includes predication information, the generation of the memory addresses in response to the second configuration information being conditioned upon the predication information.
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Abstract
The present invention includes an adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN includes a run-time configurable data path and control path. The RXN supports multi-precision arithmetic including 8, 16, 24, and 32 bit codes. Data flow can be reconfigured to minimize register accesses for different operations. For example, multiply-accumulate operations can be performed with minimal, or no, register stores by reconfiguration of the data path. Predetermined kernels can be configured during a setup phase so that the RXN can efficiently execute, e.g., Discrete Cosine Transform (DCT), Fast-Fourier Transform (FFT) and other operations. Other features are provided.
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Citations
33 Claims
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1. A reconfigurable data path circuit coupled to a memory bus for obtaining data from a memory, the reconfigurable data path circuit comprising:
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a plurality of functional units configured to perform a digital operation; one or more data address generators coupled to the memory bus; a configurable data path configurably coupled to the one or more data address generators and the plurality of functional units, the configurable data path being configurable in response to a first configuration information by configuring or reconfiguring at least one interconnection between the one or more data address generators and the plurality of functional units; wherein the one or more data address generators are coupled to the memory bus and the configurable data path, each of the one or more data address generators being configurable in response to a second configuration information that is different from the first configuration information to generate memory addresses from which data is to be read from or written to the memory for the data path configuration; and wherein the second configuration information includes predication information, the generation of the memory addresses in response to the second configuration information being conditioned upon the predication information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A digital processing system comprising:
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a memory bus coupled to a memory; and a reconfigurable data path circuit coupled to the memory bus for obtaining data from the memory, the reconfigurable data path circuit comprising; a plurality of functional units configurable to perform a digital operation; and one or more data address generators coupled to the memory bus; a configurable data path configurably coupled to the one or more data address generators and the plurality of functional units, the configurable data path being configurable in response to a first configuration information by configuring or reconfiguring at least one interconnection between the one or more data address generators and the plurality of functional units; wherein the one or more data address generators are coupled to the memory bus and the configurable data path, each of the one or more data address generators being configurable in response to a second configuration information that is different from the first configuration information to generate memory addresses from which data is to be read from or written to the memory for the data path configuration; and wherein the second configuration information includes predication information, the generation of the memory addresses in response to the second configuration information being conditioned upon the predication information. - View Dependent Claims (28, 29, 30, 31, 32, 33)
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Specification