Peripheral device, program and methods for responding to a warm reboot condition
First Claim
1. A method for responding to a warm reboot condition in a peripheral device that responds to soft resets with a PCI-E DL_DOWN command primitive, the method comprising:
- identifying a DL_DOWN command primitive in a PCI-E compatible device having a plurality of cores;
directing an input/output (I/O) port into a known state;
selectively directing a subset of the plurality of cores of the PCI-E compatible device to reset;
waiting for an indication of synchronization from the subset of the plurality of cores;
directing the subset of the plurality of cores into a non-reset condition;
waiting for an indication of synchronization from the subset of the plurality of cores; and
invoking a central processor unit reset.
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Accused Products
Abstract
A computing system peripheral device compatible with the peripheral component interconnect express (PCI-E) protocol responds to a DL_DOWN command primitive by configuring a general-purpose input/output (GPIO) port into a known state without invoking a GPIO module reset. In addition, select resources are excluded from resources on the peripheral device that are issued a reset command. The select resources can include a GPIO module, a memory element and a PCI-E SERDES module. After the remaining reset resources have completed their individual initialization processes, the central processor core on the peripheral device is reset. The described response to the DL_DOWN command primitive avoids cache data loss, masks signal transitions on I/O ports and timing problems that prevent some peripheral devices from being recognized in a computer'"'"'s basic input/output system (BIOS).
9 Citations
20 Claims
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1. A method for responding to a warm reboot condition in a peripheral device that responds to soft resets with a PCI-E DL_DOWN command primitive, the method comprising:
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identifying a DL_DOWN command primitive in a PCI-E compatible device having a plurality of cores; directing an input/output (I/O) port into a known state; selectively directing a subset of the plurality of cores of the PCI-E compatible device to reset; waiting for an indication of synchronization from the subset of the plurality of cores; directing the subset of the plurality of cores into a non-reset condition; waiting for an indication of synchronization from the subset of the plurality of cores; and invoking a central processor unit reset. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A computing system peripheral device compatible with the peripheral component interconnect express protocol, comprising:
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a peripheral component interconnect express (PCI-E) core instantiated as an application specific integrated circuit on the peripheral device; a central processor core coupled to the PCI-E core by way of a local bus, the local bus further coupling a general purpose input/output (GPIO) module, a memory element, and a PCI-E serializer/deserializer (SERDES) module to the PCI-E core and the central processor core; and a non-volatile memory element coupled to the local bus, the non-volatile memory element configured to store a set of executable instructions responsive to a DL_DOWN interrupt primitive that when executed on the peripheral device direct a GPIO port into a known state and selectively direct a subset of available resources coupled to the local bus to reset before invoking a reset of the central processor core. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A program including a set of executable instructions embodied on a computer readable storage medium, comprising:
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logic configured to identify a DL_DOWN command primitive in a PCI-E compatible core; logic configured to direct an input/output (I/O) port into a known state in response to the logic configured to identify the DL_DOWN command primitive; logic configured to selectively direct a subset of the available resources of a PCI-E compatible device to reset; logic configured to wait for an indication of synchronization from the subset of the available resources; and logic configured to invoke a central processor unit reset responsive to the indication of synchronization. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification