Method and system for instruction stuffing operations during non-intrusive digital signal processor debugging

• US 8,380,966 B2
• Filed: 11/15/2006
• Issued: 02/19/2013
• Est. Priority Date: 11/15/2006
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Codrescu, Lucian, Anderson, William C., Venkumahanti, Suresh, Giannini, Louis Achille, Pyla, Manojkumar, Chen, Xufeng
• Primary Examiner(s): LI, AIMEE J
• Application Number:
  US11/560,344
• Publication Number:
  US 20080114972A1
• Time in Patent Office: 2,288 Days
• Field of Search: 712/38, 712/32, 712/227, 714/35
• US Class Current: 712/227
• CPC Class Codes: G06F 11/362 Software debugging
• CPC Class Codes: G06F 11/3656 using a specific debug interface

Abstract

Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.

Claims

1. A method, comprising:

writing a stuff instruction at a debugging process registry associated with a debugging process, wherein the debugging process registry is associated with a core processor of a multi-threaded processor, wherein the multi-threaded processor is configured to execute a plurality of interleaved threads on the core processor, wherein each of the plurality of interleaved threads is identified by a thread number, wherein each of the plurality of interleaved threads may be executed independently and debugged independently of others of the plurality of interleaved threads, and wherein a program counter is separately maintained for each of the plurality of interleaved threads;

selecting a particular thread of the plurality of interleaved threads to execute the stuff instruction;

for the particular thread, stopping a program counter at a current program counter value during execution of the stuff instruction;

executing the stuff instruction at the particular thread of the multi-threaded processor during the debugging process; and

issuing, from the core processor, a debugging process control resume command during execution of the stuff instruction.

2. The method of claim 1, further comprising writing a stuff command at a debugging process command register associated with the debugging process registry, wherein the stuff command includes an identification of the thread number of the particular thread of the multi-threaded processor at which to execute the stuff instruction.

3. The method of claim 1, further comprising writing a stuff command at a debugging process command register associated with the debugging process registry, wherein the stuff command includes an identification of the thread number of each of more than one of the plurality of threads of the multi-threaded processor at which to execute the stuff instruction.

4. The method of claim 1, further comprising writing the stuff instruction as a branch instruction and using the current program counter value as a counter value of the branch instruction.

5. The method of claim 1, further comprising writing the stuff instruction as one of a start instruction and a resume instruction to selectively reset the particular thread of the multi-threaded processor.

6. The method of claim 1, further comprising writing the stuff instruction as a load instruction at the debugging process registry associated with the debugging process.

7. The method of claim 1, further comprising writing the stuff instruction as a register read instruction at the debugging process registry associated with the debugging process.

8. The method of claim 1, further comprising writing the stuff instruction as one of a cache read instruction and a cache write instruction at the debugging process registry associated with the debugging process.

9. The method of claim 1, further comprising writing the stuff instruction as one of a memory read instruction and a memory write instruction at the debugging process registry associated with the debugging process.

10. The method of claim 1, further comprising receiving the stuff instruction from a source that is not directly accessed by the multi-threaded processor.

11. The method of claim 10, wherein the stuff instruction is received by a joint test action group (JTAG) interface.

12. The method of claim 1, wherein the stuff instruction is unrelated to a program being debugged by the debugging process.

13. A system comprising:

a debugging process registry configured to receive a stuff instruction, wherein the debugging process registry is associated with a debugging process;

circuitry configured to execute the stuff instruction at a particular thread of a multi-threaded processor during the debugging process, wherein the multi-threaded processor is configured to execute a plurality of interleaved threads, wherein each of the plurality of interleaved threads is identified by a thread number, wherein each of the plurality of interleaved threads may be executed independently of others of the plurality of interleaved threads, and wherein a program counter is separately maintained for each of the plurality of interleaved threads;

circuitry configured to stop a program counter for the particular thread at a current program counter value during execution of the stuff instruction; and

a core processor configured to send a debugging process control resume command during execution of the stuff instruction, wherein the core processor is associated with the debugging process registry.

14. The system of claim 13, further comprising a debugging process command register associated with the debugging process registry, wherein the debugging process command register is configured to receive a stuff command in response to the stuff instruction, wherein the stuff command includes an identification of the thread number of the particular thread of the multi-threaded processor.

15. The system of claim 13, further comprising means for writing the stuff instruction as a branch instruction and using the current program counter value as a counter value of the branch instruction.

16. The system of claim 13, further comprising means for writing the stuff instruction as one of a start instruction and a resume instruction to selectively reset the particular thread of the multi-threaded processor.

17. The system of claim 13, further comprising means for writing the stuff instruction as a load instruction at the debugging process registry associated with the debugging process.

18. The system of claim 13, further comprising means for writing the stuff instruction as a register read instruction at the debugging process registry associated with the debugging process.

19. The system of claim 13, further comprising means for writing the stuff instruction as one of a cache read instruction and a cache write instruction at the debugging process registry associated with the debugging process.

20. The system of claim 13, further comprising means for writing the stuff instruction as one of a memory read instruction and a memory write instruction at the debugging process registry associated with the debugging process.

21. The system of claim 13, further comprising means for receiving the stuff instruction from a source that is not directly accessed by the multi-threaded processor.

22. A digital signal processor comprising:

means for writing a stuff instruction at a debugging process registry associated with a debugging process of the digital signal processor, wherein the digital signal processor includes a plurality of interleaved threads, wherein each of the plurality of interleaved threads is identified by a thread number, wherein each of the plurality of interleaved threads may be executed independently of others of the plurality of interleaved threads, and wherein a program counter is separately maintained for each of the plurality of interleaved threads;

means for executing the stuff instruction at a particular one of the plurality of interleaved threads of the digital signal processor during the debugging process;

means for stopping a program counter for the particular one of the plurality of interleaved threads at a current program counter value during execution of the stuff instruction; and

means for issuing, from a core processor, a debugging process control resume command during execution of the stuff instruction, wherein the core processor is associated with the debugging process registry.

23. The digital signal processor of claim 22, further comprising means for writing, in response to the stuff instruction, a stuff command at a debugging process command register associated with the debugging process registry, wherein the stuff command includes a thread number associated with the particular one of the plurality of interleaved threads.

24. The digital signal processor of claim 22, further comprising means for writing a stuff command at a debugging process command register associated with the debugging process registry, wherein the stuff command includes a thread number associated with the particular one of the plurality of interleaved threads of the digital signal processor at which to execute the stuff instruction.

25. The digital signal processor of claim 22, further comprising means for writing the stuff instruction as a branch instruction and using the current program counter value for the branch instruction counter value.

26. The digital signal processor of claim 22, further comprising means for writing the stuff instruction as one of a start instruction and a resume instruction to selectively reset the particular one of the plurality of interleaved threads.

27. The digital signal processor of claim 22, further comprising means for writing the stuff instruction as a load instruction at the debugging process registry associated with the debugging process.

28. The digital signal processor of claim 22, further comprising means for writing the stuff instruction as a register read instruction at the debugging process registry associated with the debugging process.

29. The digital signal processor of claim 22, further comprising means for writing the stuff instruction as one of a cache read instruction and a cache write instruction at the debugging process registry associated with the debugging process.

30. The digital signal processor of claim 22, further comprising means for writing the stuff instruction as one of a memory read instruction and a memory write instruction at the debugging process registry associated with the debugging process.

31. The digital signal processor of claim 22, wherein the stuff instruction is unrelated to a program being debugged by the debugging process.

32. A computer readable non-transitory medium storing processor executable instructions that, when executed by a processor, cause the processor to:

write a stuff instruction at a debugging process registry associated with a debugging process, wherein the debugging process registry is associated with a core processor of a multi-threaded processor, wherein the multi-threaded processor is configured to execute a plurality of interleaved threads on the core processor, wherein each of the plurality of interleaved threads is identified by a thread number, wherein each of the plurality of interleaved threads may be executed independently, and wherein a program counter is separately maintained for each of the plurality of interleaved threads; and

execute the stuff instruction at a particular thread of the multi-threaded processor-during the debugging process,

for the particular thread, stop a program counter at a current program counter value during execution of the stuff instruction; and

issue, from the core processor, a debugging process control resume command during execution of the stuff instruction.

33. The computer readable non-transitory medium of claim 32, further comprising instructions that, when executed by the processor, cause the processor to write a stuff command at a debugging process command register associated with the debugging process registry, wherein the stuff command includes the thread number of the particular thread of the multi-threaded processor at which to execute the stuff instruction.

34. The computer readable non-transitory medium of claim 32, further comprising instructions that, when executed by the processor, cause the processor to write the stuff instruction as one of a start instruction and a resume instruction to selectively reset the particular thread of the multi-threaded processor.

35. The computer readable non-transitory medium of claim 32, wherein the stuff instruction is unrelated to a program being debugged by the debugging process.