Method and apparatus for increased effectiveness of delay and transition fault testing
First Claim
1. A method of delay fault testing an integrated circuit comprising:
- creating a plurality of test clock gating groups, said plurality of test clock gating groups comprising elements defining signal paths between components within said integrated circuit, each of said elements of said plurality of test clock gating groups sharing clock frequency and at least one additional shared characteristic; and
selectively connecting at least one test signal through at least one low-speed gate transistor to each of said elements comprising said plurality of test clock gating groups based on membership in said test clock gating group, all members of each test clock gating group being connected to a common test signal.
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Abstract
The invention disclosed herein provides increased effectiveness of delay and transition fault testing. The method of delay fault testing integrated circuits comprises the steps of creating a plurality of test clock gating groups. The plurality of test clock gating groups comprising elements defining inter-element signal paths within the integrated circuit. Each of the elements of the plurality of test clock gating groups share clock frequency and additional shared characteristics. At least one test signal is commonly and selectively connected through at least one low-speed gate transistor to each of the elements comprising each of the plurality of test clock gating groups based on membership in the test clock gating group. This invention can also be practiced using scan-enable gating groups for the same purposes.
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Citations
25 Claims
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1. A method of delay fault testing an integrated circuit comprising:
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creating a plurality of test clock gating groups, said plurality of test clock gating groups comprising elements defining signal paths between components within said integrated circuit, each of said elements of said plurality of test clock gating groups sharing clock frequency and at least one additional shared characteristic; and selectively connecting at least one test signal through at least one low-speed gate transistor to each of said elements comprising said plurality of test clock gating groups based on membership in said test clock gating group, all members of each test clock gating group being connected to a common test signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of delay fault testing an integrated circuit comprising:
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creating a plurality of scan-enable gating groups, said plurality of scan-enable gating groups comprising elements defining signal paths between components within said integrated circuit, each of said elements of said plurality of scan-enable gating groups sharing clock frequency and at least one additional shared characteristic; and selectively connecting at least one test signal through at least one low-speed gate transistor to said elements comprising said plurality of scan-enable gating groups using low-speed gating and based on membership in said scan-enable gating group, all members of each scan-enable gating group being connected to a common test signal. - View Dependent Claims (13, 14)
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15. An integrated circuit structure comprising:
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a plurality of scan-enable gating groups, said plurality of scan-enable gating groups comprising elements defining signal paths between components within said integrated circuit, each of said elements of said plurality of scan-enable gating groups sharing clock frequency and at least one additional shared characteristic; and at least one low-speed gate transistor selectively connecting at least one test signal through to said elements; said elements comprising said plurality of scan-enable gating groups; said low speed gate transistor connected based on said elements membership in said scan-enable gating group, all members of each scan-enable gating group being connected to a common test signal. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. An integrated circuit with built-in self test structures comprising:
low speed gates for selectively gating at least one test signal to elements comprising a plurality of scan-enable gating groups, said scan-enable gating groups comprising elements defining signal paths between components of said integrated circuit and sharing clock frequency and at least one additional shared characteristic, all members of each scan-enable gating group being connected to a common test signal. - View Dependent Claims (23, 24)
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25. A program storage device readable by machine tangibly embodying a program of instructions executable by said machine for performing a method of delay fault testing of an integrated circuit, said method comprising the steps of:
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creating a plurality of test clock gating groups, said plurality of test clock gating groups comprising elements defining signal paths between components within said integrated circuit, each of said elements of said plurality of test clock gating groups sharing clock frequency and at least one additional shared characteristic; and selectively connecting at least one test signal through at least one low-speed gate transistor to each of said elements comprising said plurality of test clock gating groups based on membership in said test clock gating group, all members of each test clock gating group being connected to a common test signal.
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Specification