Structure for a duty cycle correction circuit
First Claim
1. A design structure encoded on a machine-readable data storage device, wherein the design structure is loaded from the machine-readable data storage device into a computer for generating a machine-executable representation of a duty cycle correction circuit, wherein said design structure comprises:
- a pair of first elements processed to generate a functional computer-simulated representation of a first pair of field effect transistors (FETs) having a first P-type FET and a first N-type FET;
a pair of second elements processed to generate a functional computer-simulated representation of at least two linear resistors coupled to the first pair of FETs, wherein a first linear resistor is coupled to the first P-type FET and a second linear resistor is coupled to the first N-type FET;
a third element processed to generate a functional computer-simulated representation of a first switch coupled to the first linear resistor; and
a fourth element processed to generate a functional computer-simulated representation of a second switch coupled to the second linear resistor, wherein the first, second, third, and fourth elements are configured such that an input signal is provided to the first pair of FETs and a corrected input signal is output by the at least two linear resistors, and wherein the first and second switches are selectively controlled so as to cause at least one of the first or second linear resistors to increase or decrease a duty cycle of the input signal.
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Abstract
A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.
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Citations
20 Claims
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1. A design structure encoded on a machine-readable data storage device, wherein the design structure is loaded from the machine-readable data storage device into a computer for generating a machine-executable representation of a duty cycle correction circuit, wherein said design structure comprises:
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a pair of first elements processed to generate a functional computer-simulated representation of a first pair of field effect transistors (FETs) having a first P-type FET and a first N-type FET; a pair of second elements processed to generate a functional computer-simulated representation of at least two linear resistors coupled to the first pair of FETs, wherein a first linear resistor is coupled to the first P-type FET and a second linear resistor is coupled to the first N-type FET; a third element processed to generate a functional computer-simulated representation of a first switch coupled to the first linear resistor; and a fourth element processed to generate a functional computer-simulated representation of a second switch coupled to the second linear resistor, wherein the first, second, third, and fourth elements are configured such that an input signal is provided to the first pair of FETs and a corrected input signal is output by the at least two linear resistors, and wherein the first and second switches are selectively controlled so as to cause at least one of the first or second linear resistors to increase or decrease a duty cycle of the input signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A hardware description language (HDL) design structure encoded on a machine-readable data storage device, wherein the HDL design structure is loaded from the machine-readable data storage device into a computer for generating a machine-executable representation of a duty cycle correction circuit, wherein said HDL design structure comprises:
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a pair of first elements processed to generate a functional computer-simulated representation of a first pair of field effect transistors (FETs) having a first P-type FET and a first N-type FET; a pair of second elements processed to generate a functional computer-simulated representation of at least two linear resistors coupled to the first pair of FETs, wherein a first linear resistor is coupled to the first P-type FET and a second linear resistor is coupled to the first N-type FET; a third element processed to generate a functional computer-simulated representation of a first switch coupled to the first linear resistor; and a fourth element processed to generate a functional computer-simulated representation of a second switch coupled to the second linear resistor, wherein the first, second, third, and fourth elements are configured such that an input signal is provided to the first pair of FETs and a corrected input signal is output by the at least two linear resistors, and wherein the first and second switches are selectively controlled so as to cause at least one of the first or second linear resistors to increase or decrease a duty cycle of the input signal. - View Dependent Claims (16, 17)
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18. A method in a computer-aided design system for generating a functional design model of a duty cycle correction circuit, said method comprising:
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generating a functional computer-simulated representation of a first pair of field effect transistors (FETs) having a first P-type FET and a first N-type FET; generating a functional computer-simulated representation of at least two linear resistors coupled to the first pair of FETs, wherein a first linear resistor is coupled to the first P-type FET and a second linear resistor is coupled to the first N-type FET; generating a functional computer-simulated representation of a first switch coupled to the first linear resistor; and generating a functional computer simulated representation of a fourth element processed to generate a functional computer-simulated representation of a second switch coupled to the second linear resistor, wherein the functional computer-simulated representations are configured such that an input signal is provided to the first pair of FETs and a corrected input signal is output by the at least two linear resistors, and wherein the first and second switches are selectively controlled so as to cause at least one of the first or second linear resistors to increase or decrease a duty cycle of the input signal. - View Dependent Claims (19, 20)
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Specification