Computer product, apparatus, and method for correcting time delay variation of a circuit design

• US 8,381,146 B2
• Filed: 03/16/2011
• Issued: 02/19/2013
• Est. Priority Date: 06/18/2010
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Onodera, Mitsuru
• Primary Examiner(s): DOAN, NGHIA M
• Application Number:
  US13/049,595
• Publication Number:
  US 20110314433A1
• Time in Patent Office: 706 Days
• Field of Search: 716/102, 716106-113, 716/136, 716/139, 703 13- 14, 326 21- 23, 326/25, 326 31- 34, 327/63, 327/65, 327 90- 91, 327/105, 327/107, 327108-111
• US Class Current: 716/106
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A computer-readable, non-transitory medium stores therein a design support program that causes a computer capable of accessing a storage device storing therein for each cell, an output voltage value of the cell, for each elapsed time period from a start of variation of an input voltage applied to the cell, to execute a process. The process includes extracting from the storage device, the output voltage value for each elapsed time period related to an cell under design selected from circuit information of a circuit under design; determining based on a specific voltage value, an extracted elapsed time period to be corrected; adding a time constant of an output from the cell under design to the elapsed time period determined to correction; and outputting the output voltage value for each corrected elapsed time period and the output voltage value for each elapsed time period that is not determined for correction.

Claims

1. A non-transitory computer-readable medium storing therein a design support program that causes a computer capable of accessing a storage device storing therein, for each of a plurality of cells, output voltage values for a plurality of elapsed time periods from a start time of variation of an input voltage applied to the cell, to execute a process comprising:

extracting, from the storage device, the output voltage values corresponding to a cell to be designed, the cell to be designed being selected from circuit information of a circuit to be designed;

determining, from among the elapsed time periods corresponding to the extracted output voltage values, an elapsed time period to be corrected on the basis of a specific voltage value;

correcting the elapsed time period that is determined by adding a time constant to an output side of the cell to be designed to the determined elapsed time period, the time constant being determined on the basis of wiring resistance and load capacitance of the output side of the cell to be designed; and

outputting, from among the extracted output voltage values, the output voltage value for the elapsed time period that is corrected and the second output voltage value for the elapsed time period that has not been corrected.

2. The non-transitory computer-readable medium of claim 1, the process further comprising:

identifying the elapsed time period corresponding to the output voltage value that is a threshold of an output voltage of the cell to be designed from among the output voltage values that is outputted; and

calculating a time difference between the elapsed time period from the start time of variation of the input voltage applied to the cell to be designed until the input voltage reaches a threshold of the input voltage and the elapsed time period that is identified.

3. The non-transitory computer-readable medium of claim 1, the process further comprising:

identifying the elapsed time period corresponding to the output voltage value that is a threshold of an input voltage of a cell coupled to an output of the cell to be designed from among the output voltage values that is outputted; and

calculating a time difference between the elapsed time period from the start time of variation of the input voltage applied to the cell to be designed until the input voltage reaches a threshold of the input voltage, and the elapsed time period that is identified.

4. A design support apparatus comprising:

an extracting unit configured to extract, from a storage device storing therein, for each of a plurality of cells, output voltage values for a plurality of elapsed time periods from a start time of variation of an input voltage applied to the cell, the output voltage values corresponding to a cell to be designed, the cell to be designed being selected from circuit information of a circuit to be designed,

a determining unit configured to determine, from among the elapsed time periods corresponding to the extracted output voltage values, an elapsed time period to be corrected, on the basis of a specific voltage value;

a correcting unit configured to correct the elapsed time period that is determined by adding a time constant to an output side of the cell to be designed to the determined elapsed time period, the time constant being determined on the basis of wiring resistance and load capacitance of the output side of the cell to be designed; and

an output unit configured to output, from among the extracted output voltage values, the output voltage value for the elapsed time period that is corrected by the correcting unit and the second output voltage value for the elapsed time period that has not been corrected by the correcting unit.

5. A design support method executed by a computer capable of accessing a storage device storing therein for each of a plurality of cells, output voltage values for a plurality of elapsed time periods from a start time of variation of an input voltage applied to the cell, the design support method comprising:

extracting, from the storage device, the output voltage values corresponding to a cell to be designed, the cell to be designed being selected from circuit information of a circuit to be designed;

determining, from among the elapsed time periods corresponding to the extracted output voltage values, an elapsed time period to be corrected, on the basis of a specific voltage value;

correcting the elapsed time period that is determined by adding a time constant to an output side of the cell to be designed to the determined elapsed time period, the time constant being determined on the basis of wiring resistance and load capacitance of the output side of the cell to be designed; and

outputting, from among the extracted output voltage values, the output voltage value for the elapsed time period that is corrected and the second output voltage value for the elapsed time period that has not been corrected.