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3D inter-stratum connectivity robustness

  • US 8,381,156 B1
  • Filed: 08/25/2011
  • Issued: 02/19/2013
  • Est. Priority Date: 08/25/2011
  • Status: Active Grant
First Claim
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1. A method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack, each of the two or more strata having 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements, the method comprising:

  • performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack; and

    checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack,wherein said performing step comprises one or more of;

    verifying an absence of 3D element overlapping on a same stratum side;

    verifying an absence of a customized wire or shape above a 3D terminal pin layer at a last metal layer or a last wiring metal;

    verifying pin and active element one-to-one correspondence and center-to-center alignment; and

    verifying pin matching between an abstract representation and a layout of each of the two or more strata.

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