3D inter-stratum connectivity robustness
First Claim
1. A method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack, each of the two or more strata having 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements, the method comprising:
- performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack; and
checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack,wherein said performing step comprises one or more of;
verifying an absence of 3D element overlapping on a same stratum side;
verifying an absence of a customized wire or shape above a 3D terminal pin layer at a last metal layer or a last wiring metal;
verifying pin and active element one-to-one correspondence and center-to-center alignment; and
verifying pin matching between an abstract representation and a layout of each of the two or more strata.
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Accused Products
Abstract
There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.
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Citations
22 Claims
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1. A method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack, each of the two or more strata having 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements, the method comprising:
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performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack; and checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack, wherein said performing step comprises one or more of; verifying an absence of 3D element overlapping on a same stratum side; verifying an absence of a customized wire or shape above a 3D terminal pin layer at a last metal layer or a last wiring metal; verifying pin and active element one-to-one correspondence and center-to-center alignment; and verifying pin matching between an abstract representation and a layout of each of the two or more strata. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A computer readable storage medium comprising a computer readable program stored thereon, wherein the computer readable program when executed on a computer causes the computer to perform the following:
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verify inter-stratum connectivity for two or more strata to be combined into a 3D chip stack, each of the two or more strata having 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements, wherein verify inter-stratum connectivity for two or more strata to be combined into a 3D chip stack comprises; performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack; and checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack, and wherein performing a respective 2D layout versus schematic verification comprises one or more of; verifying an absence of 3D element overlapping on a same stratum side; verifying an absence of a customized wire or shape above a 3D terminal pin layer at a last metal layer or a last wiring metal; verifying pin and active element one-to-one correspondence and center-to-center alignment; and verifying pin matching between an abstract representation and a layout of each of the two or more strata. - View Dependent Claims (21)
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22. An apparatus comprising at least a processor configured to perform the following:
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verify inter-stratum connectivity for two or more strata to be combined into a 3D chip stack, each of the two or more strata having 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements, wherein verify inter-stratum connectivity for two or more strata to be combined into a 3D chip stack comprises; perform a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack; and check inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack, wherein perform a respective 2D layout versus schematic verification comprises one or more of; verify an absence of 3D element overlapping on a same stratum side; verify an absence of a customized wire or shape above a 3D terminal pin layer at a last metal layer or a last wiring metal; verify pin and active element one-to-one correspondence and center-to-center alignment; and verify pin matching between an abstract representation and a layout of each of the two or more strata.
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Specification