Display device and manufacturing method thereof, and semiconductor device and manufacturing method thereof

• US 8,383,468 B2
• Filed: 04/05/2012
• Issued: 02/26/2013
• Est. Priority Date: 06/17/2008
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yagi, Iwao
• Primary Examiner(s): Thai, Luan C
• Application Number:
  US13/440,648
• Publication Number:
  US 20120190145A1
• Time in Patent Office: 327 Days
• Field of Search: 438/155, 438/158, 438/149, 438/637
• US Class Current: 438/155
• CPC Class Codes: G02F 1/133305 Flexible substrates, e.g. plastics, organic film
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133555 Transflectors
• CPC Class Codes: G02F 1/136218 Shield electrodes
• CPC Class Codes: H10K 19/10 comprising field-effect transistors

Abstract

A method of forming a display device including source/drain electrodes on a substrate, a pixel electrode, an insulating partition wall layer, a channel-region semiconductor layer. Source/drain electrodes of a thin-film transistor are formed on the substrate, while a pixel electrode is connected to the source/drain electrodes. The insulating partition wall layer is formed on the substrate, where the partition wall layer has a first opening extending to between the source electrode and the drain electrode. Furthermore, a channel-region semiconductor layer is formed by depositing a semiconductor layer over the partition wall layer. The channel-region semiconductor layer is on the bottom of the first opening to be separate from a upper part of the partition wall layer.

Claims

1. A method of manufacturing a display device, comprising the steps of:

forming source/drain electrodes of a thin-film transistor on a substrate, while forming a pixel electrode connected to the source/drain electrodes;

forming an insulating partition wall layer on the substrate, where the partition wall layer has a first opening extending to between the source electrode and the drain electrode; and

forming a channel-region semiconductor layer by depositing a semiconductor layer over the partition wall layer,

wherein

the channel-region semiconductor layer is on the bottom of the first opening to be separate from a upper part of the partition wall layer, and

the first opening is formed with reversely tapered side walls.

2. The method of claim 1, wherein the partition wall layer has a second opening located on the pixel electrode and extending to the pixel electrode.

3. The method of claim 2, further comprising the steps of:

forming a semiconductor layer made of a same material as that of the channel-region semiconductor layer on the bottom of the second opening; and

removing the semiconductor layer from the bottom of the second opening after said step of forming the channel-region semiconductor layer.

4. The method of claim 1, wherein the step of forming a channel-region semiconductor layer comprises:

employing a technique of selectively preparing a solution containing a semiconductor material on the bottom of the first opening only; and

forming the channel-region semiconductor layer constructed of the semiconductor material on the bottom of the first opening.