High-density nonvolatile memory and methods of making the same

• US 8,383,478 B2
• Filed: 08/01/2011
• Issued: 02/26/2013
• Est. Priority Date: 12/19/2002
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Herner, Scott Brad, Mahajani, Maitreyee
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US13/195,518
• Publication Number:
  US 20110287615A1
• Time in Patent Office: 575 Days
• Field of Search: 438257-258, 438/593, 257/530, 257313-316, 367/65, 367/117, 367/14
• US Class Current: 438/257
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 27/148 Charge coupled imagers individual charge coupled devices H01L29/765
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.

Claims

1. A method to form a nonvolatile memory cell, the method comprising:

i) forming a first conductor at a first height above a substrate;

ii) forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type;

iii) forming a first antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and

iv) forming a second conductor above the first antifuse.

2. The method of claim 1, wherein forming the first semiconductor element comprises:

after forming the first conductor, depositing a semiconductor layer stack on the first conductor; and

patterning and etching the semiconductor layer stack to form the first pillar-shaped semiconductor element.

3. The method of claim 2, wherein depositing the semiconductor layer stack comprises depositing polycrystalline silicon.

4. The method of claim 1, wherein the substrate comprises monocrystalline silicon.

5. The method of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.

6. The method of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

7. The method of claim 1, wherein the third heavily doped layer is doped by ion implantation.

8. The method of claim 1, wherein the first heavily doped layer is doped by in situ doping.

9. The method of claim 1, wherein forming the first conductor comprises:

depositing a first tungsten layer; and

patterning and etching the first tungsten layer to form the first conductor.

10. The method of claim 1, wherein the first antifuse comprises an oxide layer.

11. The method of claim 10, wherein the oxide layer comprises silicon dioxide.