Method of forming a compliant monopolar micro device transfer head with silicon electrode

• US 8,383,506 B1
• Filed: 07/06/2012
• Issued: 02/26/2013
• Est. Priority Date: 07/06/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: LuxVue Techonology Corporation (Apple Inc.)
• Inventors: Golda, Dariusz, Bibl, Andreas
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US13/543,690
• Time in Patent Office: 235 Days
• Field of Search: 438/703, 438/739, 257/619, 257/623, 257/774
• US Class Current: 438/619
• CPC Class Codes: B81C 99/002 Apparatus for assembling MEMS, e.g. micromanipulators micromanipulators per se B25J7/00
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/7598 specially adapted for batch processes
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors

Abstract

A compliant monopolar micro device transfer head array and method of forming a compliant monopolar micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array including a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect, and each silicon electrode is deflectable into a cavity between the base substrate and the silicon electrode. A dielectric layer covers a top surface of each mesa structure.

Claims

1. A method of forming a compliant micro device transfer head array comprising:

etching a top silicon layer of a silicon-on-insulator stack to form an array of silicon electrodes electrically connected with a silicon interconnect, each silicon electrode including an electrode lead and a mesa structure that protrudes above the silicon interconnect;

forming a dielectric layer over the array of silicon electrodes; and

etching one or more cavities in the base substrate directly underneath the array of silicon electrodes such that each silicon electrode in the array of silicon electrodes is deflectable into the one or more cavities.

2. The method of claim 1, wherein etching one or more cavities in the base substrate comprises reactive ion etching with a fluorinated plasma selected from the group consisting of SF₆ and XeF₂.

3. The method of claim 1, wherein etching one or more cavities in the base substrate comprises etching a separate cavity in the base substrate directly underneath each silicon electrode in the array of silicon electrodes.

4. The method of claim 1, wherein etching one or more cavities in the base substrate comprises etching a single cavity in the base substrate directly underneath each silicon electrode in the array of silicon electrodes.

5. The method of claim 4, further comprising etching the single cavity in the base substrate such that it wraps around an end of the silicon interconnect.

6. The method of claim 1, wherein etching the top silicon layer of the silicon-on-insulator stack exposes a buried oxide layer.

7. The method of claim 6, further comprising forming a patterned layer over the buried oxide layer and the dielectric layer after forming the dielectric layer over the array of silicon electrodes and the second array of silicon electrodes, and etching through the buried oxide layer to expose a portion of the base substrate.

8. The method of claim 7, further comprising etching the one or more cavities in the base substrate directly underneath the array of silicon electrodes using the dielectric layer as an etching mask.

9. The method of claim 6, wherein forming the dielectric layer comprises thermal oxidation of the array of silicon electrodes.

10. The method of claim 6, further comprising etching a backside via opening through the base substrate directly underneath the silicon interconnect.

11. The method of claim 10, further comprising, forming a passivation layer within via opening, wherein forming the passivation layer comprises simultaneously thermally oxidizing the array of silicon electrodes and the base substrate within the via opening.

12. The method of claim 11, further comprising forming a patterned conductive layer within the via opening to make electrical contact with the silicon interconnect.

13. The method of claim 12, wherein forming the patterned conductive layer comprises depositing the patterned conductive layer through a shadow mask.

14. The method of claim 7, further comprising etching through the dielectric layer to expose a portion of the silicon interconnect simultaneously with etching through the buried oxide layer to expose the portion of the base substrate.

15. The method of claim 14, further comprising etching a topside via opening through the exposed portion of the silicon interconnect and the buried oxide layer, and forming a patterned conductive layer within the topside via opening to make electrical contact with the silicon interconnect.

16. The method of claim 7, further comprising etching through the dielectric layer to expose each of the mesa structures simultaneously with etching through the buried oxide layer to expose the portion of the base substrate.

17. The method of claim 16, further comprising forming a patterned second dielectric layer over each of the mesa structures.

18. The method of claim 17, wherein forming the patterned second dielectric layer comprises blanket depositing the second dielectric layer, and removing a portion of the second dielectric layer.

19. The method of claim 18, wherein blanket depositing the second dielectric layer comprises atomic layer deposition.

20. The method of claim 7, further comprising etching through the dielectric layer to expose a portion of the silicon interconnect and each of the mesa structures simultaneously with etching through the buried oxide layer to expose a portion of the base substrate.

21. The method of claim 20, further comprising forming a patterned second dielectric layer over each of the mesa structures.

22. The method of claim 21, further comprising etching a topside via opening through the exposed portion of the silicon interconnect and the buried oxide layer, and forming a patterned conductive layer within the topside via opening to make electrical contact with the silicon interconnect.

23. The method of claim 22, wherein etching the one or more cavities further comprises using the second dielectric layer formed over each of the mesa structures and the conductive layer formed within the topside via opening as an etching mask.