Method for making multilayer connection structure

• US 8,383,512 B2
• Filed: 05/24/2011
• Issued: 02/26/2013
• Est. Priority Date: 01/19/2011
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Shih-Hung, Lue, Hang-Ting, Lee, Hong-Ji, Yang, Chin-Cheng
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US13/114,931
• Publication Number:
  US 20120181701A1
• Time in Patent Office: 644 Days
• Field of Search: 438/637, 438/652, 438/622, 438/675, 257/E21.159
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/60 Peripheral circuit regions
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2^N contact levels. Each mask is used to etch effectively half of the contact openings. When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls.

Claims

1. A method, for use with a three-dimensional stacked IC device having a stack of at least 4 contact levels at an interconnect region, for creating interconnect contact regions aligned with and exposing landing areas at the contact levels, each contact level comprising a conductive layer and an insulation layer, the method comprising:

removing at least a portion of any upper layer overlying the interconnect region to expose a first contact level and create contact openings for each contact level;

selecting a set of N etch masks for creating a plurality of levels of interconnect contact regions at the stack of the contact levels, N being an integer equal to at least 2;

using the N masks to etch the contact openings up to and including 2^N contact levels, the N masks using step comprising;

using a first mask to etch one contact level for effectively half of the contact openings;

using a second mask to etch two contact levels for effectively half of the contact openings; and

the removing, selecting and using steps being carried out so that the contact openings extend to the 2^N contact levels; and

whereby electrical conductors can be formed through the contact openings to contact the landing areas at the contact levels.

2. The method according to claim 1, wherein the removing step is carried out using an additional mask.

3. The method according to claim 1, wherein:

the first mask using step comprises using the first mask to etch one contact level at every other contact opening; and

the second mask using step comprises using the second mask to etch two contact levels at third and fourth contact openings in at least one set of first through fourth contact openings.

4. The method according to claim 1, wherein the N masks using step further comprises:

using a third mask to etch four contact levels for effectively half of the contact openings; and

using a fourth mask to etch eight contact levels for effectively half of the contact openings.

5. The method according to claim 4, wherein:

the third mask using step comprises using the third mask to etch four contact levels at fifth through eighth contact openings in at least one set of first through eighth contact openings; and

the fourth mask using step comprises using the fourth mask to etch eight contact levels at ninth through 16th contact openings in at least one set of first through 16th contact openings.

6. The method according to claim 4, wherein:

the first mask using step is carried out to etch one contact level at contact openings 2, 4, 6, 8, 10, 12, 14, 16;

the second mask using step is carried out to etch two contact levels at contact openings 3, 4, 7, 8, 11, 12, 15, 16;

the third mask using step is carried out to etch four contact levels at contact openings 5-8, 13-16; and

the fourth mask is carried out to etch eight contact levels at contact openings 9-16.

7. The method according to claim 4, wherein:

the first mask using step is carried out to etch eight contact levels at contact openings 2, 4, 6, 8, 10, 12, 14, 16;

the second mask using step is carried out to etch two contact levels at contact openings 5, 6, 7, 8, 13, 14, 15, 16;

the third mask using step is carried out to etch four contact levels at contact openings 3, 4, 7, 8, 11, 12, 15, 16; and

the fourth mask is carried out to etch one contact level at contact openings 9-16.

8. The method according to claim 1, further comprising:

creating a ground contact opening through the contact levels; and

forming an electrical ground conductor through the ground contact opening to make electrical contact with a plurality of the conductive layers of the contact levels.

9. The method according to claim 8, wherein the ground contact opening has a ground opening sidewall, and further comprising:

removing portions of the insulation layers at the ground contact opening sidewall prior to the electrical ground conductor forming step so the electrical ground conductor makes enhanced electrical contact between the electrical ground conductor and the plurality of the conductive layers of the contact levels.

10. The method according to claim 1, wherein the using step is carried out in other than the order of the number of contact levels etched.

11. The method according to claim 1, wherein the contact openings have sidewalls, and further comprising forming a dielectric layer on the sidewalls.

12. A method for providing electrical connections to landing areas at a stack of contact levels of an interconnect region for a three-dimensional stacked IC device of a type comprising an interconnect region, the interconnect region including an upper layer with a stack of contact levels beneath the upper layer, each contact level comprising a conductive layer and an insulation layer, the method comprising:

removing at least a portion of any upper layer overlying the interconnect region to expose a first contact level and create contact openings for each contact level;

selecting a set of N etch masks for creating a plurality of levels of interconnect contact regions at the stack of the contact levels, N being an integer equal to at least 2;

using the N masks to etch the contact openings up to and including 2^N contact levels, the N masks using step comprising;

using a first mask to etch one contact level for effectively half of the contact openings;

using a second mask to etch two contact levels for effectively half of the contact openings; and

the removing selecting and using steps being carried out so that the contact openings define sidewalls and extend to the 2^N contact levels;

forming a dielectric layer on the sidewalls; and

forming electrical conductors through the contact openings to the landing areas at the contact levels, the dielectric layers electrically insulating the electrical conductors from the sidewalls.

13. The method according to claim 12, further comprising:

creating a ground contact opening through the contact levels; and

forming an electrical ground conductor through the ground contact opening to make electrical contact with a plurality of the conductive layers of the contact levels.

14. The method according to claim 13, wherein the ground contact opening has a ground contact opening sidewall, and further comprising:

removing portions of the insulation layers at the ground contact opening sidewall prior to the electrical ground conductor forming step so that portions of a plurality of the conductive layers adjacent to the ground contact opening are exposed, whereby the electrical ground conductor makes enhanced electrical contact with the plurality of the conductive layers.

15. The method according to claim 12, further comprising forming contact opening extensions in an upper layer overlying the interconnect region, and wherein the electrical conductors forming step is carried out with a first part of the electrical conductors extending through the contact levels and a second part of the electrical conductors extending through the upper layer.

16. The method according to claim 15, wherein the electrical conductors forming step is carried out with the first and second parts being of different electrically conductive materials.