Field effect transistor using oxide semicondutor and method for manufacturing the same

• US 8,384,077 B2
• Filed: 12/10/2008
• Issued: 02/26/2013
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Idemitsu Kosan Company Limited
• Original Assignee: Idemitsu Kosan Company Limited
• Inventors: Yano, Koki, Kawashima, Hirokazu, Inoue, Kazuyoshi, Tomai, Shigekazu, Kasami, Masashi
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US12/747,573
• Publication Number:
  US 20100289020A1
• Time in Patent Office: 1,539 Days
• Field of Search: 257/43, 257/57, 257/59
• US Class Current: 257/43
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A field effect transistor which includes, on a substrate, at least a semiconductor layer, a passivation layer for the semiconductor layer, a source electrode, a drain electrode, a gate insulating film and a gate electrode, the source electrode and the drain electrode being connected through the semiconductor layer, the gate insulating film being present between the gate electrode and the semiconductor layer, the passivation layer being at least on one surface side of the semiconductor layer, and the semiconductor layer including a composite oxide which comprises In (indium), Zn (zinc) and Ga (gallium) in the following atomic ratios (1) to (3):
In/(In+Zn)=0.2 to 0.8  (1)
In/(In+Ga)=0.59 to 0.99  (2)
Zn/(Ga+Zn)=0.29 to 0.99  (3).

Claims

1. A field effect transistor which comprises, on a substrate, at least a semiconductor layer, a passivation layer, a source electrode, a drain electrode, a gate insulating film and a gate electrode,

the source electrode and the drain electrode being connected to each other through the semiconductor layer,

the gate insulating film being present between the gate electrode and the semiconductor layer,

the passivation layer being at least on one surface side of the semiconductor layer, and

the semiconductor layer comprising a composite oxide which comprises In (indium), Zn (zinc) and Ga (gallium) in the following atomic ratios (1) to (3):

In/(In+Zn)=0.2 to 0.8 

 

(1)

In/(In+Ga)=0.59 to 0.99 

 

(2)

Zn/(Ga+Zn)=0.29 to 0.99 

 

(3),

wherein the semiconductor layer is an amorphous film which has an energy width (E₀) on the non-localized level of 14 meV or less.

2. The field effect transistor according to claim 1, wherein the composite oxide further satisfies the following atomic ratio (4):

Ga/(In+Zn+Ga)=0.01 to 0.2 

 

(4).

3. The field effect transistor according to claim 1, wherein the semiconductor layer is an amorphous film which keeps at least part of the edge-sharing structure of a bixbyite structure of indium oxide.

4. The field effect transistor according to claim 1, which has a field effect mobility of 1 cm²/Vs or more, an on off ratio of 10⁶ or more, an off current of 1 pA or less, an S value of 0.8 V/dec or less, a threshold voltage of 0 V or more and 10 V or less, and an amount of shift in threshold voltage before and after application of a 10 μ

A-direct voltage at 50°

C. for 100 hours of 1.5 V or less.

5. The field effect transistor according to claim 1, which has a structure for shielding the semiconductor layer from light.

6. The field effect transistor according to claim 1, wherein the passivation layer for the semiconductor layer comprises an amorphous oxide or an amorphous nitride.

7. The field effect transistor according to claim 1, wherein at least one of the source electrode, the drain electrode and the gate electrode comprises an alloy containing copper.

8. The field effect transistor according to claim 1, which further comprises a contact layer between the semiconductor layer and at least one of the source electrode, the drain electrode and the gate electrode.

9. The field effect transistor according to claim 1, which further comprises an oxide resistant layer having a resistance higher than that of the semiconductor layer between the semiconductor layer and the gate insulating film and/or between the semiconductor layer and the passivation layer.

10. The field effect transistor according to claim 1, wherein the semiconductor layer further comprises one or more elements selected from the group consisting of Sn (tin), Ge (germanium), Si (silicon), Ti (titanium), Zr (zirconium) and Hf (hafnium) in an amount of 100 to 10000 atomic ppm.

11. A method for producing the field effect transistor according to claim 1, comprising the steps of forming a semiconductor layer by DC or AC sputtering by using a sintered target of a composite oxide and conducting a heat treatment at 70 to 350°

C. after the formation of the semiconductor layer and a passivation layer for the semiconductor layer.

12. A liquid crystal display or an organic electroluminescence display using the field effect transistor according to claim 1.