Oxide semiconductor device
First Claim
1. A semiconductor device comprising:
- a gate electrode layer over an insulating surface;
a gate insulating layer over the gate electrode layer;
an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer including a channel formation region overlapping with the gate electrode layer;
an oxide insulating layer over the gate electrode layer with the oxide semiconductor layer interposed therebetween, the oxide insulating layer being in contact with a first region of the oxide semiconductor layer;
a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and
an insulating layer over the source electrode layer and the drain electrode layer,wherein the oxide semiconductor layer comprises a second region in contact with the source electrode layer or the drain electrode layer, and a third region in contact with the insulating layer, andwherein the third region is located between the first region and the second region.
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Accused Products
Abstract
An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.
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Citations
27 Claims
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1. A semiconductor device comprising:
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a gate electrode layer over an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer including a channel formation region overlapping with the gate electrode layer; an oxide insulating layer over the gate electrode layer with the oxide semiconductor layer interposed therebetween, the oxide insulating layer being in contact with a first region of the oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and an insulating layer over the source electrode layer and the drain electrode layer, wherein the oxide semiconductor layer comprises a second region in contact with the source electrode layer or the drain electrode layer, and a third region in contact with the insulating layer, and wherein the third region is located between the first region and the second region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A semiconductor device comprising:
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a gate electrode layer over an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer; a first oxide insulating layer over the oxide semiconductor layer; a second oxide insulating layer above and in contact with the gate insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; and an insulating layer over the source electrode layer and the drain electrode layer, wherein the oxide semiconductor layer comprises a first region in contact with the first oxide insulating layer, a second region in contact with the source electrode layer or the drain electrode layer, and a third region in contact with the insulating layer, wherein, in the first region, a channel formation region overlaps with the gate electrode layer with the gate insulating layer interposed therebetween, wherein the third region is located between the channel formation region and the second region, wherein a stacked layer, formed of the gate insulating layer and the second oxide insulating layer, is interposed between a first electrically conductive layer and a second electrically conductive layer; wherein the first electrically conductive layer is located below the stacked layer and formed from a same layer as the gate electrode layer; and wherein the second electrically conductive layer is located over the stacked layer and formed from a same layer as the source electrode layer. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A semiconductor device comprising:
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a gate electrode layer over an insulating surface; a gate insulating layer over the gate electrode layer; an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer including a channel formation region overlapping with the gate electrode layer; an oxide insulating layer over the gate electrode layer with the oxide semiconductor layer interposed therebetween, the oxide insulating layer being in contact with a first region of the oxide semiconductor layer; a source electrode layer and a drain electrode layer each consisting essentially of metal and over the oxide semiconductor layer; and an insulating layer over the source electrode layer and the drain electrode layer, wherein the oxide semiconductor layer comprises a second region in contact with the source electrode layer or the drain electrode layer, and a third region in contact with the insulating layer, and wherein the third region is located between the first region and the second region. - View Dependent Claims (25, 26, 27)
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Specification