Method of fabricating vertical structure LEDs

• US 8,384,120 B2
• Filed: 03/14/2011
• Issued: 02/26/2013
• Est. Priority Date: 04/09/2002
• Status: Expired due to Term

• Current Assignee: Suzhou Lekin Semiconductor Company Limited
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Lee, Jong-Lam, Jeong, In-kwon, Yoo, Myung Cheol
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US13/047,371
• Publication Number:
  US 20110193128A1
• Time in Patent Office: 715 Days
• Field of Search: 257/79, 257/99, 257/103, 257/E33.025
• US Class Current: 257/99
• CPC Class Codes: H01C 7/006 Thin film resistors
• CPC Class Codes: H01C 7/008 Thermistors H01C7/02 - H01C7/06 take precedence
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 33/0025 comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/36 characterised by the electrodes
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/40 Materials therefor
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: Y10S 438/958 Passivation layer
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.

Claims

1. A semiconductor light-emitting device, comprising:

a conductive support structure;

a semiconductor structure over the conductive support structure, the semiconductor structure having a first surface, a second surface, and two side surfaces in a vertical cross-section, wherein the semiconductor structure comprises a first-type semiconductor layer, an active layer, and a second-type semiconductor layer, wherein the second surface is opposite the first surface, wherein the first surface, relative to the second surface, is proximate to the conductive support structure, and wherein the second surface is a dominant light emitting surface;

a first electrode electrically connected to the first-type semiconductor layer, wherein the first electrode is arranged between the conductive support structure and the first surface of the semiconductor structure;

a second electrode electrically connected to the second-type semiconductor layer, wherein the second electrode is arranged over a part of the second surface; and

a passivation layer contacting the second surface and the two side surfaces of the semiconductor structure,

wherein the passivation layer has a first length in contact with the first-type semiconductor layer and a second length in contact with the second-type semiconductor layer, and wherein the second length is greater than the first length, and

wherein the passivation layer has an open space on the second surface, and wherein the open space is aligned with the second electrode.

2. The device according to claim 1, further comprising a metallic pad over the second electrode, wherein the metallic pad is arranged higher than the portion of the passivation layer contacting the second surface.

3. The device according to claim 1, wherein the passivation layer is arranged over a part of the second electrode.

4. The device according to claim 1, wherein the passivation layer contacting the side surface of the semiconductor structure extends to the second surface of the semiconductor structure.

5. The device according to claim 1, wherein the conductive support structure comprises a metal layer including one of Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, and Al.

6. The device according to claim 1, wherein the passivation layer is further arranged partially between the conductive support structure and the semiconductor structure.

7. The device according to claim 1, wherein the first electrode contacts the first surface of the semiconductor structure, and wherein a contact area between the first electrode and the first surface of the semiconductor structure is smaller than the entire area of the first surface of the semiconductor structure.

8. A semiconductor light-emitting device, comprising:

a conductive support structure;

a semiconductor structure over the conductive support structure, the semiconductor structure having a first surface, a second surface, and two side surfaces in a vertical cross-section, wherein the semiconductor structure comprises a first-type semiconductor layer, an active layer, and a second-type semiconductor layer, wherein the second surface is opposite the first surface, and wherein the first surface, relative to the second surface, is proximate to the conductive support structure, wherein the active layer has a third surface contacting the first-type semiconductor structure and the first-type semiconductor layer has a fourth surface contacting the active layer, and wherein the area of the fourth surface is the same as the third surface;

a first electrode electrically connected to the first-type semiconductor layer, wherein the first electrode is arranged between the conductive support structure and the first surface of the semiconductor structure;

a second electrode electrically connected to the second-type semiconductor layer, wherein the second electrode has an area that is smaller than the area of the second surface; and

a passivation layer contacting the second surface and the two side surfaces of the semiconductor structure,

wherein the passivation layer has a first length in contact with the first-type semiconductor layer and a second length in contact with the second-type semiconductor layer, and wherein the second length is greater than the first length.

9. The device according to claim 8, further comprising a metallic pad over the second electrode, wherein the metallic pad is arranged higher than the portion of the passivation layer contacting the second surface.

10. The device according to claim 8, wherein the passivation layer is arranged over a part of the second electrode.

11. The device according to claim 8, wherein the passivation layer contacting the side surface of the semiconductor structure extends to the second surface of the semiconductor structure.

12. The device according to claim 8, wherein the conductive support structure comprises a metal layer including one of Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, and Al.

13. The device according to claim 8, wherein the passivation layer is further arranged partially between the conductive support structure and the semiconductor structure.

14. The device according to claim 8, wherein the passivation layer has an open space on the second surface, and wherein the open space is aligned with the second electrode.

15. A semiconductor light-emitting device, comprising:

a conductive support structure;

a semiconductor structure over the conductive support structure, the semiconductor structure having a first surface, a second surface, and two side surfaces in a vertical cross-section, wherein the semiconductor structure comprises a first-type semiconductor layer, an active layer, and a second-type semiconductor layer, wherein the second surface is opposite the first surface, and wherein the first surface, relative to the second surface, is proximate to the conductive support structure, wherein the second surface is a dominant light emitting surface;

a first electrode electrically connected to the first-type semiconductor layer, wherein the first electrode is arranged between the conductive support structure and the first surface of the semiconductor structure;

a second electrode electrically connected to the second-type semiconductor layer, wherein the second electrode has an area that is smaller than the area of the second surface; and

a passivation layer contacting the second surface and the two side surfaces of the semiconductor structure,

wherein the passivation layer has a first length in contact with the first-type semiconductor layer and a second length in contact with the second-type semiconductor layer, and wherein the second length is greater than the first length.

16. The device according to claim 15, further comprising a metallic pad over the second electrode, wherein the metallic pad is arranged higher than the portion of the passivation layer contacting the second surface.

17. The device according to claim 15, wherein the passivation layer is arranged over a part of the second electrode.

18. The device according to claim 15, wherein the passivation layer contacting the side surface of the semiconductor structure extends to the second surface of the semiconductor structure.

19. The device according to claim 15, wherein the conductive support structure comprises a metal layer including one of Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, and Al.

20. The device according to claim 15, wherein the passivation layer is further arranged partially between the conductive support structure and the semiconductor structure.