Device having adjustable channel stress and method thereof

• US 8,384,162 B2
• Filed: 05/16/2011
• Issued: 02/26/2013
• Est. Priority Date: 12/06/2010
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Xu, Qiuxia, Chen, Dapeng, Yin, Huaxiang
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US13/108,742
• Publication Number:
  US 20120139054A1
• Time in Patent Office: 652 Days
• Field of Search: 257/369, 257/288, 257/E29.255, 257/E21.409, 257/E21.635, 257/E27.062, 438/197, 438/199
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate

Abstract

The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device (200, 300), comprising a semiconductor substrate (202, 302); a channel formed on the semiconductor substrate (202, 302); a gate dielectric layer (204, 304) formed on the channel; a gate conductor (206, 306) formed on the gate dielectric layer (204, 304); and a source and a drain formed on both sides of the gate; wherein the gate conductor (206, 306) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

Claims

1. An MOS device (200, 300), comprising:

a semiconductor substrate (202, 302);

a channel formed on the semiconductor substrate (202, 302);

a gate dielectric layer (204, 304) formed on the channel;

a gate conductor (206, 306) formed on the gate dielectric layer (204, 304); and

a source and a drain formed on both sides of the gate;

wherein the gate conductor (206, 306) has a shape in the form of a regular trapezoid if the MOS device is a NMOS device or an inverted trapezoid if the MOS device is a PMOS device, for adjust stress to be applied to the channel so as to adjust the mobility of carriers in the channel.

2. The MOS device of claim 1, further comprising at least one of stress sidewalls (207, 307) formed on both sides of the gate conductor for generating a second stress to be applied to the channel, a stress source (208, 308) embedded into the source and drain areas for generating a third stress to be applied to the channel, and a stress liner (210, 310) formed on the MOS device (200, 300) for generating a fourth stress to be applied to the channel such that the mobility of carriers in the channel of the MOS device is enhanced.

3. The MOS device of claim 2, wherein the MOS device is an NMOS device, the first stress produced by the gate conductor is tensile stress, and the second stress, the third stress, and the fourth stress are tensile stresses or compressive stresses, such that the sum of the first stress, the second stress, the third stress, and the fourth stress is adjusted to be tensile stress.

4. The MOS device of claim 3, wherein an angle α

between side and bottom of the regular trapezoid satisfies 45°

<

a<

90°

.

5. The MOS device of claim 4, wherein α

satisfies 45°

<

a<

85°

.

6. The MOS device of claim 5, wherein α

satisfies 45°

<

a<

75°

.

7. The MOS device of claim 1, the gate dielectric layer (204, 304) includes one of SiO₂, SiON, ZrO₂, HfO₂, Al₂O₃, HfSiO, HfAlO, HfSiON, HfAlSiO, HfTaSiO and/or combination thereof, and/or multi-layer structures thereof.

8. The MOS device of claim 1, the gate conductor includes one of polysilicon, metal or metal alloy, silicide, conductive Nitride, and poly-SiGe, or the combinations thereof.

9. The MOS device of claim 2, the stress sidewalls (207, 307) are formed of one of SiO₂, Silicon Nitride, SiO₂/Silicon Nitride, the multi-layer structure of shift SiO₂ or Silicon Nitride and the conventional SiO₂ or Silicon Nitride, and the multi-layer structure of shift SiO₂ or Silicon Nitride and a first conventional SiO2 or Nitride and a second conventional SiO₂ or Silicon Nitride.

10. The MOS device of claim 2, the stress source (208, 308) includes SiC or SiGe.

11. The MOS device of claim 2, the stress liner (210, 310) is nitride or oxide liner.