High performance system-on-chip using post passivation process

• US 8,384,189 B2
• Filed: 08/06/2008
• Issued: 02/26/2013
• Est. Priority Date: 03/29/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shing
• Primary Examiner(s): ARMAND, MARC ANTHONY
• Application Number:
  US12/186,530
• Publication Number:
  US 20080284032A1
• Time in Patent Office: 1,665 Days
• Field of Search: 257/759, 257/E23.161, 257/E21.022, 257/528, 257/379, 257/758, 257/760
• US Class Current: 257/528
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Claims

1. An integrated circuit chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure, and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said passivation layer comprises a nitride layer;

a first polymer layer over said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers;

a patterned circuit layer on said first polymer layer and over said passivation layer, wherein said patterned circuit layer is connected to said first contact point through said first opening, wherein said patterned circuit layer comprises a coil connected to said first contact point through said first opening and connected to said second contact point through said second opening, wherein said coil comprises an electroplated metal; and

a second polymer layer over said patterned circuit layer.

2. The integrated circuit chip of claim 1, wherein said electroplated metal of said coil comprises electroplated gold.

3. The integrated circuit chip of claim 1, wherein said first polymer layer comprises polyimide.

4. The integrated circuit chip of claim 1, wherein said passivation layer further comprises an oxide layer under said nitride layer.

5. The integrated circuit chip of claim 1, wherein said passivation layer has a thickness less than said thickness of said first polymer layer.

6. The integrated circuit chip of claim 1, wherein said second polymer layer comprises polymide.

7. An integrated circuit chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a separating layer over said metallization structure, and said first and second dielectric layers, wherein a first opening in said separting layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said separting layer comprises a nitride layer;

a first polymer layer over said separting layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers;

a patterned circuit layer on said first polymer layer and over said separting layer, wherein said patterned circuit layer is connected to said first contact point through said first opening, wherein said patterned circuit layer comprises a coil connected to said first contact point through said first opening and connected to said second contact point through said second opening, wherein said coil comprises electroplated copper; and

a second polymer layer over said patterned circuit layer.

8. The integrated circuit chip of claim 7, wherein said first polymer layer comprises polyimide.

9. The integrated circuit chip of claim 7, wherein said separting layer further comprises an oxide layer under said nitride layer.

10. The integrated circuit chip of claim 7, wherein said separating layer has a thickness less than said thickness of said first polymer layer.

11. The integrated circuit chip of claim 7, wherein said second polymer layer comprises polyimide.

12. An integrated circuit chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first dielectric layer over said silicon substrate;

a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure, and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said passivation layer comprises a nitride layer;

a first polymer layer over said passivation layer, wherein said first polymer layer has a thickness between 2 and 150 micrometers;

a patterned circuit layer on said first polymer layer and over said passivation layer, wherein said patterned circuit layer is connected to said first contact point through said first opening, wherein said patterned circuit layer comprises a coil connected to said first contact point through said first opening and connected to said second contact point through said second opening, wherein said coil comprises gold; and

a second polymer layer over said patterned circuit layer.

13. The integrated circuit chip of claim 12, wherein said passivation layer has a thickness less than said thickness of said first polymer layer.

14. The integrated circuit chip of claim 12, wherein said second polymer layer comprises polyimide.

15. An integrated circuit chip comprising:

a silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises an aluminum-containing layer;

a separating layer over said metallization structure, wherein a first opening in said separating layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said separating layer comprises an oxide layer;

a patterned circuit layer over said separating layer, wherein said patterned circuit layer comprises a coil and a metal line, wherein said coil comprises a portion spaced apart from said metal line, wherein said coil is connected to said first contact point through said first opening, wherein said metal line is connected to said second contact point through said second opening, wherein said patterned circuit layer comprises electroplated copper; and

a first dielectric layer over said metal line.

16. The integrated circuit chip of claim 15 further comprising a polymer layer over said separating layer, wherein said patterned circuit layer is further on said polymer layer.

17. The integrated circuit chip of claim 15 further comprising a second dielectric layer over said separating layer, wherein said patterned circuit layer is further on said second dielectric layer.

18. The integrated circuit chip of claim 15, wherein said separating layer further comprises a nitride layer.

19. The integrated circuit chip of claim 15, wherein said first dielectric layer comprises a polymer.

20. The integrated circuit chip of claim 15, wherein a third opening in said separating layer is over a third contact point of said metallization structure, and said third contact point is at a bottom of said third opening, wherein said coil is connected to said third contact point through said third opening.

21. The integrated circuit chip of claim 17, wherein said second dielectric layer comprises a polymer layer having a thickness between 2 and 150 micrometers and greater than that of said separating layer.