Method and system for identifying counterfeit programmable logic devices

• US 8,384,415 B2
• Filed: 02/15/2012
• Issued: 02/26/2013
• Est. Priority Date: 02/15/2011
• Status: Active Grant

• Current Assignee: Mercury Defense Systems, Inc. (Mercury Systems, Incorporated)
• Original Assignee: James M Lewis
• Inventors: Lewis, James M.
• Primary Examiner(s): LE, DON P
• Application Number:
  US13/397,232
• Publication Number:
  US 20120212253A1
• Time in Patent Office: 377 Days
• Field of Search: 326/8, 326/37, 326/38, 326/54, 708/490, 708/530
• US Class Current: 326/8
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

A method for combating counterfeiting and tampering of integrated circuits includes the steps providing a programmable logic device, the programmable logic device including an arithmetic circuit implemented into the substrate, and constructing an arithmetic feedback oscillator using the arithmetic circuit. The step of constructing the arithmetic feedback oscillator includes incorporating a feedback loop into the arithmetic circuit and feeding output bits back into an input of the arithmetic circuit. The method also includes the step of selecting input values producing repeating values in a lesser order bit of a product of the arithmetic circuit when first and second input are applied to the arithmetic circuit and monitoring the lesser order bit and determining a predicted pattern.

Claims

1. A method for combating counterfeiting and tampering of integrated circuits,

comprising:

providing a programmable logic device, the programmable logic device including a multiplier implemented into the substrate;

constructing a multiplier feedback oscillator using the multiplier wherein the step of constructing the multiplier feedback oscillator includes incorporating a feedback loop into the multiplier and feeding least significant product bits back into one of operand inputs;

selecting input values producing repeating values in a lesser order bit of a product of the multiplier when first and second operands are applied to the multiplier;

monitoring the lesser order bit and determining a predicted pattern.

2. The method according to claim 1, including the further steps of obtaining a test integrated circuit and testing to determine if the predicted pattern is produced by the test integrated circuit.

3. The method according to claim 1, wherein the lesser order bit is the zeroth product bit, the 1^st product bit or the 2^nd product bit.

4. The method according to claim 1, wherein the multiplier is a binary multiplier.

5. The method according to claim 1, wherein the feedback loop includes a multiplexer.

6. The method according to claim 1, wherein two'"'"'s complement signed multiplication is employed in the multiplier.

7. The method according to claim 1, further including a binary counter associated with each output bit of the multiplier feedback oscillator.

8. The method according to claim 7, wherein each binary counter receives output bits of the multiplier feedback oscillator for evaluating the frequency of change of the output bits of the multiplier.

9. The method according to claim 8, wherein each of the binary counters produces a time interval over which the bit counters are allowed to operate.

10. The method according to claim 1, further including a register connected to outputs of the multiplier to evaluate the output of the ring oscillator.

11. The method according to claim 1, wherein a time interval generated by a clock or a binary counter is used to control the rate at which data is latched into the register.

12. A method for combating counterfeiting and tampering of integrated circuits, comprising:

providing a programmable logic device, the programmable logic device including an arithmetic circuit implemented into the substrate;

constructing an arithmetic feedback oscillator using the arithmetic circuit wherein the step of constructing the arithmetic feedback oscillator includes incorporating a feedback loop into the arithmetic circuit and feeding output bits back into an input of the arithmetic circuit;

selecting input values producing repeating values in a lesser order bit of a product of the arithmetic circuit when first and second input are applied to the arithmetic circuit;

monitoring the lesser order bit and determining a predicted pattern.

13. The method according to claim 12, wherein the arithmetic circuit is a binary adder.

14. The method according to claim 12, wherein the arithmetic circuit is a binary divider.

15. The method according to claim 14, wherein the feedback loop includes an XOR function.

16. The method according to claim 14, wherein the feedback loop includes a logic function.

17. The method according to claim 14, wherein the feedback loop includes an binary adder.

18. The method according to claim 12, wherein the arithmetic circuit is a binary multiplier.

19. The method according to claim 12, wherein the arithmetic circuit is an Arithmetic Logic Unit.

20. The method according to claim 12, wherein the feedback loop includes a multiplexer.

21. The method according to claim 12, further including a binary counter associated with each output bit of the arithmetic feedback oscillator.

22. The method according to claim 21, wherein each binary counter receives output bits of the arithmetic feedback oscillator for evaluating the frequency of change of the output bits of the arithmetic circuit.

23. The method according to claim 21, wherein each of the binary counters produces a time interval over which the bit counters are allowed to operate.

24. The method according to claim 12, further including a register connected to outputs of the arithmetic circuit to evaluate the output of the arithmetic feedback oscillator.