Configuring multiple programmable logic devices with serial peripheral interfaces

• US 8,384,427 B1
• Filed: 04/01/2010
• Issued: 02/26/2013
• Est. Priority Date: 04/01/2010
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Tang, Howard, Spinti, Roger
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US12/752,455
• Time in Patent Office: 1,062 Days
• Field of Search: 326 38- 47
• US Class Current: 326/39
• CPC Class Codes: H03K 19/1776 for memories

Abstract

In one embodiment, a programmable logic device includes configuration memory, an SPI port for receiving a bitstream, a chip select output pin, and configuration control circuitry. The chip select output pin can provide a chip select signal having a first logic state for selecting another device (such as another PLD) to receive a bitstream and a second logic state for de-selecting the other device. The configuration control circuitry is responsive to a command embedded in the received bitstream to drive the chip select output pin from the second logic state to the first logic state, thereby selecting the other device to receive the bitstream. Several such PLDs connected in a daisy chain can thus be configured from a single configuration source or have their configuration data read back while so connected.

Claims

1. A programmable logic device (PLD) comprising:

configuration memory;

a serial peripheral interface (SPI) port for receiving a bitstream, the bitstream including at least commands;

a chip select output pin for providing a chip select signal having a first logic state for selecting another device to receive the bitstream at an SPI port of the other device and a second logic state for de-selecting the other device; and

configuration control circuitry within the PLD coupled to the SPI port and the chip select output pin, the configuration control circuitry responsive to a command embedded in the received bitstream to drive the chip select output pin from the second logic state to the first logic state.

2. The PLD of claim 1, wherein the configuration control circuitry is also responsive to the embedded command to stop the PLD from responding to a read back command following the embedded command in the bitstream.

3. The PLD of claim 1, wherein the bitstream is a configuration bitstream, and the SPI port is adapted to receive a configuration bitstream that includes configuration data for configuring the configuration memory.

4. The PLD of claim 3, wherein the configuration control circuitry is also responsive to the embedded command to stop configuration data following the embedded command in the configuration bitstream from configuring the configuration memory.

5. The PLD of claim 1, wherein the SPI port includes a chip select input pin for receiving a chip select signal having a first logic state for selecting the PLD to receive the bitstream and a second logic state for de-selecting the PLD.

6. The PLD of claim 1, wherein the SPI port is a slave SPI port that includes a chip select input pin to receive a chip select signal and the bitstream from a master SPI port of a CPU.

7. The PLD of claim 1, wherein the other device is another PLD.

8. The programmable logic device of claim 1, including:

a plurality of configuration pins for receiving configuration signals that set a configuration mode for the device, one of the configuration modes being an SPI configuration mode,

wherein the configuration control circuitry is coupled to the configuration pins and responsive to the configuration control signals.

9. Programmable logic devices comprising:

a first programmable logic device (PLD) including;

configuration memory;

a serial peripheral interface (SPI) port for receiving a bitstream, the bitstream including at least commands;

a chip select output pin for providing a chip select signal having a first logic state for selecting a second PLD to receive the bitstream at an SPI port of the second PLD and a second logic state for de-selecting the second PLD; and

configuration control circuitry within the PLD coupled to the SPI port and the chip select output pin, the configuration control circuitry responsive to a command embedded in the received bitstream to drive the chip select output pin from the second logic state to the first logic state; and

a second PLD including;

configuration memory;

a serial peripheral interface (SPI) port for receiving a bitstream to configure the second PLD, the bitstream including at least commands;

a chip select input pin for receiving a chip select signal having a first logic state for selecting the second PLD to receive the bitstream at the SPI port of the second PLD and a second logic state for de-selecting the second PLD; and

configuration control circuitry within the PLD coupled to the SPI port, the configuration control circuitry responsive to the received bitstream.

10. The PLDs of claim 9, wherein the chip select input pin of the second PLD is coupled to receive a chip select signal from the chip select output pin of the first PLD.

11. The PLDs of claim 9 including a CPU having an SPI port, wherein the first PLD is coupled to receive the bitstream from the SPI port of the CPU, and the second PLD is coupled to receive a chip select signal from the first PLD and the bitstream from the SPI port of the CPU.

12. A method of configuring multiple programmable logic devices (PLDs) connected in a daisy chain, the method comprising:

providing first and second PLDs, each PLD including an SPI port for receiving a configuration bitstream to configure the PLD, the configuration bitstream including commands and configuration data;

transmitting the configuration bitstream concurrently to the SPI ports of the first and second PLDs; and

in response to a command embedded in the configuration bitstream received by the first and second PLDs;

stopping from within the first PLD configuration data following the embedded command in the configuration bitstream from configuring the first PLD; and

driving from within the first PLD a chip select signal from the first PLD to the second PLD to select the second PLD for configuration with the configuration data following the embedded command.

13. The method of claim 12, wherein the configuration bitstream contains first configuration data followed by the embedded command followed by second configuration data, the method including configuring the first PLD with the first configuration data before responding to the embedded command.

14. The method of claim 13, including configuring the second PLD with the second configuration data after responding to the embedded command.

15. The method of claim 12, wherein the first PLD generates the chip select signal transmitted from the first PLD to the second PLD.

16. The method of claim 12, wherein the chip select signal is transmitted by the first PLD from a chip select output pin of the first PLD to a chip select input pin of the second PLD.

17. The method of claim 12 including, before the embedded command in the configuration bitstream is received by the first PLD:

transmitting a chip select signal to the first PLD to select the first PLD for configuration by configuration data preceding the embedded command; and

transmitting a chip select signal from the first PLD to the second PLD to de-select the second PLD for configuration by the preceding configuration data.

18. The method of claim 17, wherein:

the chip select signal for the first PLD is transmitted to a chip select input pin of the first PLD; and

the chip select signal for the second PLD is transmitted by the first PLD from a chip select output pin of the first PLD to a chip select input pin of the second PLD.

19. The method of claim 12, including:

before transmitting the configuration bitstream to the PLD, determining from the configuration signals sent to the PLD that the PLD is in an SPI configuration mode.

20. A method of reading back configuration data from multiple programmable logic devices (PLDs) connected in a daisy chain, the method comprising:

providing first and second PLDs, each PLD including an SPI port for receiving for receiving a bitstream that includes at least one command, wherein a chip select output pin of the first PLD is coupled to a chip select input pin of the second PLD;

transmitting a chip select signal to a chip select input pin of the first PLD but not to the chip select input pin of the second PLD;

transmitting the bitstream concurrently to the SPI ports of the first and second PLDs; and

in response to at least one command embedded in the bitstream received by the first and second PLDs;

transmitting configuration data in the first PLD to be read back;

stopping the first PLD from responding to a read back command following the at least one embedded command in the bitstream; and

driving from within the first PLD a chip select signal from the chip select output pin of the first PLD to the chip select input pin of the second PLD to select the second PLD,

wherein the second PLD once selected responds to the read back command following the at least one embedded command in the bitstream.