Power amplifier with improved bandwidth

• US 8,384,484 B2
• Filed: 06/10/2011
• Issued: 02/26/2013
• Est. Priority Date: 02/11/2011
• Status: Active Grant

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: MACOM Technology Solutions Holdings, Inc.
• Inventors: Winslow, Thomas A.
• Primary Examiner(s): Nguyen, Khanh V
• Application Number:
  US13/157,602
• Publication Number:
  US 20120206206A1
• Time in Patent Office: 627 Days
• Field of Search: 330/192, 330/195, 330/302
• US Class Current: 330/302
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 3/195 in integrated circuits

Abstract

An amplifier output impedance matching configuration including a first impedance transformer and one or more second impedance transformers. The first impedance transformer receives input signals from a power amplifier and generates output signals to a load. The one or more second impedance transformers are connected between the first impedance transformer and the load through which the output signals are passed.

Claims

1. An amplifier output impedance matching configuration comprising:

a first broadside coupled impedance transformer receiving an input signal from a power amplifier and generating an output signal to a load; and

one or more second broadside coupled impedance transformers connected between said first broadside coupled impedance transformer and said load through which said output signal is passed.

2. The amplifier output impedance matching configuration according to claim 1, wherein said power amplifier comprises a monolithic microwave integrated circuit (MMIC) compatible amplifier.

3. The amplifier output impedance matching configuration according to claim 1, wherein said power amplifier, said first broadside coupled impedance transformer, and said one or more second broadside coupled impedance transformers are disposed on a monolithic microwave integrated circuit (MMIC).

4. The amplifier output impedance matching configuration according to claim 1, wherein at least one of said first and said second broadside coupled impedance transformers comprises a broadside coupled structure and a compensating structure configured to reduce a half-wavelength resonance of said broadside coupled structure.

5. The amplifier output impedance matching configuration according to claim 1, further comprising a series capacitor block connected between said first broadside coupled impedance transformer and said one or more second broadside coupled impedance transformers.

6. The amplifier output impedance matching configuration according to claim 1, wherein said power amplifier comprises a multi-octave high-power amplifier.

7. The amplifier output impedance matching configuration according to claim 1, wherein at least one of said one or more second broadside coupled impedance transformers provides electrostatic discharge (ESD) protection to a lead connected to said load.

8. The amplifier output impedance matching configuration according to claim 7, wherein said lead connected to said load comprises a radio frequency (RF) lead.

9. The amplifier output impedance matching configuration according to claim 1, wherein said load is biased through said first and said second broadside coupled impedance transformers.

10. The amplifier output impedance matching configuration according to claim 1, wherein said power amplifier comprises a large periphery amplifier combining a plurality of power field effect transistors (FETs) and said load has an impedance of about 50 ohms.

11. A method of output matching a power amplifier on a monolithic microwave integrated circuit comprising:

disposing said power amplifier circuit on a substrate of said monolithic microwave integrated circuit; and

disposing an output impedance matching network on said substrate of said monolithic microwave integrated circuit, wherein said output impedance matching network comprises at least two broadside coupled impedance transformers connected in series between an output of said power amplifier circuit and a load.

12. The method according to claim 11, wherein one or more of said at least two broadside coupled impedance transformers each comprise a broadside coupled structure and a compensating structure configured to reduce a half-wavelength resonance of said broadside coupled structure.

13. The method according to claim 11, wherein said output impedance matching network on said substrate of said monolithic microwave integrated circuit further comprises a series capacitor block coupling said at least two broadside coupled impedance transformers.

14. The method according to claim 11, wherein said power amplifier comprises a multi-octave high-power amplifier.

15. The method according to claim 11, wherein said at least two broadside coupled impedance transformers provides electrostatic discharge (ESD) protection to a lead connected to said load.

16. The method according to claim 15, wherein said lead connected to said load comprises a radio frequency (RF) lead.

17. The method according to claim 11, further comprising biasing said load through one or more of said at least two broadside coupled impedance transformers.

18. The method according to claim 11, wherein said power amplifier comprises a large periphery amplifier combining a plurality of power field effect transistors (FETs) and said load has an impedance of about 50 ohms.

19. The method according to claim 18, wherein said output impedance matching network comprises:

a first impedance transforming stage coupled to said plurality of power FETs and comprising a plurality of broadside coupled transformers connected in parallel; and

a second impedance transforming stage coupled to said load and comprising at least one broadside coupled transformer, wherein said first and said second impedance transforming stages are connected in series.

20. The method according to claim 11, wherein said output impedance matching network comprises:

a first impedance transforming stage comprising a plurality of broadside coupled transformers connected in parallel; and

a second impedance transforming stage coupled in series with said first impedance transforming stage and comprising at least one broadside coupled transformer.