Orthogonally referenced integrated ensemble for navigation and timing

• US 8,384,487 B2
• Filed: 04/08/2011
• Issued: 02/26/2013
• Est. Priority Date: 04/08/2011
• Status: Active Grant

• Current Assignee: UT-Battelle LLC
• Original Assignee: UT-Battelle LLC
• Inventors: Smith, Stephen Fulton, Moore, James Anthony
• Primary Examiner(s): Chang, Joseph
• Application Number:
  US13/083,366
• Publication Number:
  US 20120256694A1
• Time in Patent Office: 690 Days
• Field of Search: 331/158, 331/176
• US Class Current: 331/158
• CPC Class Codes: G01C 21/10 by using measurements of speed or acceleration G01C21/24, G01C21/26 take precedence
• CPC Class Codes: G01P 15/097 by vibratory elements
• CPC Class Codes: G01P 15/18 in two or more dimensions
• CPC Class Codes: G01S 1/045 Receivers
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03B 5/30 with frequency-determining element being electromechanical resonator
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03K 3/01 Details
• CPC Class Codes: H03L 1/028 of generators comprising piezoelectric resonators H03L1/021, H03L1/022 take precedence; oscillation generators with a piezoelectric resonator H03B5/32
• CPC Class Codes: H03L 5/00 Automatic control of voltage, current, or power
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation

Abstract

An orthogonally referenced integrated ensemble for navigation and timing includes a dual-polyhedral oscillator array, including an outer sensing array of oscillators and an inner clock array of oscillators situated inside the outer sensing array. The outer sensing array includes a first pair of sensing oscillators situated along a first axis of the outer sensing array, a second pair of sensing oscillators situated along a second axis of the outer sensing array, and a third pair of sensing oscillators situated along a third axis of the outer sensing array. The inner clock array of oscillators includes a first pair of clock oscillators situated along a first axis of the inner clock array, a second pair of clock oscillators situated along a second axis of the inner clock array, and a third pair of clock oscillators situated along a third axis of the inner clock array.

Claims

1. A dual-mode oscillator, comprising:

a crystal operable to oscillate in a main mode and in a temperature-measurement mode;

a first linear gain-controlled oscillator circuit operable to generate a main signal of the main mode from the crystal;

a second linear gain-controlled oscillator circuit operable to generate a temperature-measurement signal of the temperature-measurement mode from the crystal; and

a signal processor coupled to the first linear gain-controlled oscillator circuit and the second linear gain-controlled oscillator circuit, the signal processor configured to generate an output signal based on the main signal and the temperature-measurement signal;

wherein the temperature-measurement mode comprises a fifth-overtone mode.

2. The dual-mode oscillator according to claim 1, wherein the main mode comprises a third-overtone C mode and the temperature-measurement mode comprises a fifth-overtone B mode.

3. The dual-mode oscillator according to claim 1, wherein the crystal comprises a doubly-rotated stress-compensated cut crystal.

4. The dual-mode oscillator according to claim 1, wherein the crystal comprises a doubly rotated IT-cut crystal.

5. The dual-mode oscillator according to claim 1, wherein the first linear gain-controlled oscillator circuit and the second linear gain-controlled oscillator circuit are disposed in a symmetrical differential layout.

6. The dual-mode oscillator according to claim 1, wherein the first linear gain-controlled oscillator circuit and the second linear gain-controlled oscillator circuit each comprises a feedback network operable to regulate oscillator loop gain.

7. The dual-mode oscillator according to claim 6, wherein the feedback network comprises a plurality of resistors coupled in series.

8. The dual-mode oscillator according to claim 6, wherein the feedback network comprises an isolation hybrid RF-style combiner.

9. The dual-mode oscillator according to claim 1, wherein the first linear gain-controlled oscillator circuit and the second linear gain-controlled oscillator circuit each comprises a balanced bridge network operable to regulate oscillator loop gain.

10. The dual-mode oscillator according to claim 9, wherein the balanced bridge network includes a single-ended gain-control device to regulate the oscillator loop gain.

11. The dual-mode oscillator according to claim 10, wherein the single-ended gain control device comprises a junction gate field-effect transistor.

12. The dual-mode oscillator according to claim 1, wherein the first linear gain-controlled oscillator circuit and the second linear gain-controlled oscillator circuit each comprises a transformer.

13. The dual-mode oscillator according to claim 1, wherein the first linear gain-controlled oscillator circuit and the second linear gain-controlled oscillator circuit each comprises a plurality of inductors operable to provide alternating current isolation.

14. The dual-mode oscillator according to claim 1, further comprising a bias string coupled to the second linear gain-controlled, oscillator circuit, the bias string operable to provide temperature compensation of a bias current, the bias string comprising a plurality of diode-connected, transistors.