Method for making high-performance RF integrated circuits

• US 8,384,508 B2
• Filed: 03/31/2011
• Issued: 02/26/2013
• Est. Priority Date: 09/04/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): Musleh, Mohamad
• Assistant Examiner(s): H., R.
• Application Number:
  US13/077,009
• Publication Number:
  US 20110175195A1
• Time in Patent Office: 698 Days
• Field of Search: 438/113, 438/114, 336/200, 336/223, 336/232, 336/206, 336/65, 336/208, 257/531, 257758-759
• US Class Current: 336/200
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1423 Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created on the passive surface of the substrate close to and on each side of the scribe line. A layer of insulation is deposited, a layer of dielectric is deposited over the layer of insulation, at least one bond pad is provided on the surface of the layer of dielectric on each side of the scribe line. At least one inductor is created on each side of the scribe line on the surface of the layer of dielectric. A layer of passivation is deposited over the layer of dielectric. The substrate is attached to a glass panel by interfacing the surface of the layer of passivation with the glass panel. The substrate is sawed from the backside of the substrate in alignment with the scribe line. The silicon that remains in place in the passive surface of the substrate underneath the scribe lines is removed by etching, the glass panel is separated along the scribe line. Under the second embodiment of the invention, the inductor is created on the surface of a thick layer of polymer that is deposited over the layer of passivation.

Claims

1. A semiconductor device comprising:

a silicon substrate;

an insulating layer over said silicon substrate;

an interconnecting structure over said insulating layer, wherein said interconnecting structure comprises a damascene copper interconnect;

a first dielectric layer between a first interconnect line of said interconnecting structure and a second interconnect line of said interconnecting structure, wherein said interconnecting structure comprises a via in said first dielectric layer and between said first and second interconnect lines, wherein said first interconnect line is connected to said second interconnect line through said via;

a contact pad comprising a portion not vertically over said silicon substrate, wherein said contact pad is configured for connecting to a surrounding circuit; and

a second dielectric layer over said first dielectric layer, said interconnecting structure and said contact pad.

2. The semiconductor device of claim 1 further comprising an inductor over said first dielectric layer.

3. The semiconductor device of claim 1 further comprising an inductor under said second dielectric layer.

4. The semiconductor device of claim 1, wherein said second dielectric layer comprises an oxide.

5. The semiconductor device of claim 1, wherein said second dielectric layer comprises a nitride.

6. The semiconductor device of claim 1, wherein said second dielectric layer comprises a polymer.

7. The semiconductor device of claim 1, wherein said first dielectric layer comprises a nitride.

8. The semiconductor device of claim 1, wherein said first dielectric layer comprises an oxide.

9. The semiconductor device of claim 1, wherein said first dielectric layer comprises an oxynitride.

10. The semiconductor device of claim 1 further comprising a glass substrate over said second dielectric layer.

11. A circuit component comprising:

a structure comprising a silicon substrate having an active-surface region, multiple active devices in or on said active-surface region, an insulating layer over said silicon substrate, an interconnecting structure over said insulating layer, a dielectric layer between a first interconnect line of said interconnecting structure and a second interconnect line of said interconnecting structure, wherein said interconnecting structure comprises a via in said dielectric layer and between said first and second interconnect lines, wherein said first interconnect line is connected to said second interconnect line through said via, a contact pad comprising a portion not vertically over said silicon substrate, wherein said contact pad is configured for connecting to a surrounding circuit, and a passivation layer over said dielectric layer, said first and second interconnect lines and said contact pad; and

a glass substrate joining said structure.

12. The circuit component of claim 11, wherein said passivation layer comprises an oxide.

13. The circuit component of claim 11, wherein said passivation layer comprises a nitride.

14. The circuit component of claim 11, wherein said dielectric layer comprises a nitride.

15. The circuit component of claim 11, wherein said dielectric layer comprises an oxynitride.

16. The circuit component of claim 11, wherein said dielectric layer comprises an oxide.

17. The circuit component of claim 11, wherein said interconnecting structure comprises a damascene copper interconnect.

18. The circuit component of claim 11, wherein said interconnecting structure comprises an aluminum interconnect.

19. The circuit component of claim 11 further comprising an adhesive layer joining said glass substrate and said structure.

20. The circuit component of claim 11, wherein said structure further comprises an inductor under said passivation layer.

21. The circuit component of claim 11, wherein said structure further comprises an inductor over said dielectric layer.

22. The circuit component of claim 11, wherein said contact pad is at a bottom of said dielectric layer.

23. A circuit component comprising:

a structure comprising a silicon substrate having an active-surface region, multiple active devices in or on said active-surface region, an insulating layer over said silicon substrate, an interconnecting structure over said insulating layer, a dielectric layer between a first interconnect line of said interconnecting structure and a second interconnect line of said interconnecting structure, wherein said interconnecting structure comprises a via in said dielectric layer and between said first and second interconnect lines, wherein said first interconnect line is connected to said second interconnect line through said via, wherein said interconnecting structure comprises a damascene copper interconnect, and a passivation layer over said dielectric layer and said interconnecting structure; and

a glass substrate joining said structure.

24. The circuit component of claim 23, wherein said passivation layer comprises an oxide.

25. The circuit component of claim 23, wherein said passivation layer comprises a nitride.

26. The circuit component of claim 23, wherein said dielectric layer comprises a nitride.

27. The circuit component of claim 23, wherein said dielectric layer comprises an oxynitride.

28. The circuit component of claim 23, wherein said dielectric layer comprises an oxide.

29. The circuit component of claim 23, wherein said structure further comprises a contact pad at a bottom of said dielectric layer, wherein said contact pad comprises a portion not vertically over said silicon substrate, wherein said contact pad is configured for connecting to a surrounding circuit.

30. The circuit component of claim 23 further comprising an adhesive layer joining said glass substrate and said structure.

31. The circuit component of claim 23, wherein said structure further comprises an inductor under said passivation layer.

32. The circuit component of claim 23, wherein said structure further comprises an inductor over said dielectric layer.

33. A circuit component comprising:

a first structure comprising a silicon substrate having an active-surface region, multiple active devices in or on said active-surface region, an insulating layer over said silicon substrate, an interconnecting structure over said insulating layer, a dielectric layer between a first interconnect line of said interconnecting structure and a second interconnect line of said interconnecting structure, wherein said interconnecting structure comprises a via in said dielectric layer and between said first and second interconnect lines, wherein said first interconnect line is connected to said second interconnect line through said via, an inductor over said dielectric layer, wherein there is no active device vertically under said inductor, wherein said inductor comprises damascene copper, and a passivation layer over said dielectric layer, said interconnecting structure and said inductor; and

a second structure joining said first structure.

34. The circuit component of claim 33, wherein said passivation layer comprises an oxide.

35. The circuit component of claim 33 wherein said passivation layer comprises a nitride.

36. The circuit component of claim 33, wherein said dielectric layer comprises a nitride.

37. The circuit component of claim 33, wherein said dielectric layer comprises an oxynitride.

38. The circuit component of claim 33, wherein said dielectric layer comprises an oxide.

39. The circuit component of claim 33, wherein said first structure further comprises a contact pad at a bottom of said dielectric layer, wherein said contact pad comprises a portion not vertically over said silicon substrate, wherein said contact pad is configured for connecting to a surrounding circuit.

40. The circuit component of claim 33 further comprising an adhesive layer joining said second structure and said first structure.

41. The circuit component of claim 33 wherein said second structure comprises a glass substrate.