Non-volatile memory device having stacked structure, and memory card and electronic system including the same

• US 8,385,122 B2
• Filed: 01/14/2010
• Issued: 02/26/2013
• Est. Priority Date: 01/14/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Won-joo, Park, Yoon-dong, Sung, Jung-hun, Kyoung, Yong-koo, Choi, Sang-moo, Lee, Tae-hee
• Primary Examiner(s): BERNSTEIN, ALLISON
• Application Number:
  US12/656,043
• Publication Number:
  US 20100177566A1
• Time in Patent Office: 1,139 Days
• Field of Search: 365/185.11, 365/185.17, 257314-316, 257/686, 257/E29.3
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set.

Claims

1. A non-volatile memory device having a stacked structure, the non-volatile memory device comprising:

a stacked NAND cell array having at least one NAND set, the at least one NAND set including a plurality of NAND strings, each of the NAND strings including a plurality of string selection transistors, and a number of NAND strings of the at least one NAND set being 2^k and a number of string selection transistors of each of the NAND strings being m (m=2×

k, k>

2); and

at least one signal line commonly coupled with the at least one NAND set.

2. The non-volatile memory device of claim 1, further comprising:

a substrate, wherein the plurality of NAND strings is vertically stacked on the substrate and the at least one signal line is on the substrate.

3. The non-volatile memory device of claim 2, wherein the at least one signal line includes a bit line connected to one end of the at least one NAND set.

4. The non-volatile memory device of claim 3, wherein the at least one signal line further includes at least one common source line connected to another end of the at least one NAND set.

5. The non-volatile memory device of claim 3, wherein the at least one signal line further includes a plurality of word lines coupled with the at least one NAND set.

6. The non-volatile memory device of claim 5, wherein

each of the NAND strings includes a plurality of memory cells, and

the plurality of word lines are coupled with the plurality of memory cells of the at least one NAND set.

7. The non-volatile memory device of claim 3, wherein the at least one signal line further includes a plurality of string selection lines coupled with the at least one NAND set.

8. The non-volatile memory device of claim 7, wherein

the plurality of string selection lines are coupled with the plurality of string selection transistors of the at least one NAND set.

9. The non-volatile memory device of claim 3, wherein the at least one signal line further includes at least one ground selection line coupled with the at least one NAND set.

10. The non-volatile memory device of claim 9, wherein

each of the NAND strings includes at least one ground selection transistor, and

the at least one ground selection line is coupled with the at least one ground selection transistor of the at least one NAND set.

11. The non-volatile memory device of claim 2, wherein the at least one NAND set includes a plurality of NAND sets arranged on the substrate in a row.

12. The non-volatile memory device of claim 11, wherein

the at least one signal line includes a plurality of bit lines, and

the plurality of bit lines is connected to the plurality of NAND sets.

13. The non-volatile memory device of claim 12, wherein

the at least one signal line further includes a plurality of string selection lines, a plurality of word lines, at least one ground selection line, and a common source line, and

the plurality of string selection lines, the plurality of word lines, the at least one ground selection line, and the common source line are coupled with the plurality of NAND sets.

14. The non-volatile memory device of claim 2, wherein the at least one signal line is under the stacked NAND cell array.

15. The non-volatile memory device of claim 14, wherein the at least one signal line is coupled with the at least one NAND set via at least one vertical plug on the substrate.

16. The non-volatile memory device of claim 2, wherein the at least one signal line includes

at least one bit line under the stacked NAND cell array and on the substrate, and

a plurality of string selection lines, a plurality of word lines, at least one ground selection line, and a common source line which are under the stacked NAND cell array and on the at least one bit line.

17. The non-volatile memory device of claim 2, further comprising:

a core circuit unit on the substrate, wherein the core circuit unit is electrically connected to the at least one signal line.

18. The non-volatile memory device of claim 17, wherein

the at least one signal line is under the stacked NAND cell array, and

the core circuit unit and the at least one signal line are connected to each other only under the stacked NAND cell array.

19. The non-volatile memory device of claim 18, wherein the core circuit unit includes a row decoder connected to a plurality of string selection lines, a plurality of word lines, and at least one ground selection line.

20. The non-volatile memory device of claim 18, wherein

the at least one signal line includes at least one bit line and the core circuit unit includes a column decoder connected to the at least one bit line.

21. The non-volatile memory device of claim 18, wherein the core circuit unit includes

a row decoder connected to a portion of the at least one signal line,

a column decoder connected to another portion of the at least one signal line,

a sense amplifier coupled with the column decoder,

a page buffer coupled with one of the sense amplifier and the column decoder, and

a control logic coupled with the row decoder, the column decoder, and the page buffer.

22. The non-volatile memory device of claim 2, wherein

the at least one signal line includes a bit line connected to one end of the at least one NAND set and a plurality of string selection lines coupled with the plurality of string selection transistors of the at least one NAND set, and

the plurality of string selection transistors of each the NAND strings includes at least one depletion-mode string selection transistor.

23. The non-volatile memory device of claim 22, wherein a number of string selection transistors of each of the NAND strings is less than a number of NAND strings of the at least one NAND set.

24. The non-volatile memory device of claim 22, wherein the string selection transistors of each of the NAND strings includes k enhancement-mode string selection transistors and k depletion-mode string selection transistors.

25. The non-volatile memory device of claim 22, wherein each of the string selection lines is coupled with 2^k−

1 enhancement-mode string selection transistors of the at least one NAND set.

26. A non-volatile memory device having a stacked structure, the non-volatile memory device comprising:

a plurality of NAND blocks stacked on a substrate, wherein each of the NAND blocks includes the non-volatile memory device of claim 1, the plurality of NAND strings of each of the NAND blocks being vertically stacked on the substrate, and the at least one signal line is on the substrate.

27. The non-volatile memory device of claim 26, wherein the at least one signal line of a lower most NAND block from among the plurality of NAND blocks includes at least one bit line under the stacked NAND cell array of the lower most NAND block and on the substrate, and connected to the at least one NAND set of the lower most NAND block.

28. The non-volatile memory device of claim 27, wherein the at least one signal line of the lower most NAND block from among the plurality of NAND blocks includes at least one common source line under the stacked NAND cell array of the lower most NAND block and on the substrate, and connected to the at least one NAND set of the lower most NAND block.

29. The non-volatile memory device of claim 27, wherein the at least one signal line of each NAND block includes a plurality of string selection lines, a plurality of word lines, at least one ground selection line, and at least one common source line.

30. A memory card comprising:

a memory unit including the non-volatile memory device of claim 1; and

a controller unit configured to control the memory unit.

31. An electronic system comprising:

a memory unit including the non-volatile memory device of claim 1;

a processor unit communicating with the memory unit via a bus; and

an input/output device communicating with the bus.