Structure and method for biasing phase change memory array for reliable writing

• US 8,385,141 B2
• Filed: 08/30/2011
• Issued: 02/26/2013
• Est. Priority Date: 01/19/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US13/221,711
• Publication Number:
  US 20110310662A1
• Time in Patent Office: 546 Days
• Field of Search: 365/148, 365/163, 365/189.16, 365/220
• US Class Current: 365/189.16
• CPC Class Codes: G11C 11/21 using electric elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays

Abstract

A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.

Claims

1. In an integrated circuit comprising an array of memory cells each comprising a phase change material, a structure for simultaneously writing a plurality of bits to the array of memory cells comprising:

a plurality of pulse control structures acting simultaneously, each of the pulse control structures able to operate in three modes,

a first mode in which the pulse control structure provides a high current of short duration to one of the memory cells,

a second mode in which the pulse control structure provides a current lower than the high current and of longer duration than the short duration to one of the memory cells, and

a third mode in which the pulse control structure provides no current to one of the memory cells, wherein each of the plurality of pulse control structures provides an output signal received by a plurality of driver circuits, each of the driver circuits selecting the output signal if selected by a decoder signal selecting the driver circuit.

2. The structure of claim 1, wherein the plurality of bits are in memory cells in a plurality of memory layers of the memory array.

3. The structure of claim 1, wherein the current lower than the high current is less than 60% of the high current.

4. The structure of claim 3, wherein the current lower than the high current is less than 50% of the high current.

5. The structure of claim 1, wherein the longer duration is more than twice the short duration.

6. The structure of claim 5, wherein the longer duration is about five times as long as the short duration.

7. The structure of claim 1, wherein each of the memory cells each comprising a phase change material also further comprises a diode in series with the phase change material.

8. In an integrated circuit comprising an array of memory cells each comprising a phase change material, a structure for simultaneously writing a plurality of bits to the array of memory cells comprising:

a plurality of pulse control structures acting simultaneously, each of the pulse control structures able to operate in three modes,

a first mode in which the pulse control structure provides a high current of short duration to one of the memory cells,

a second mode in which the pulse control structure provides a current lower than the high current and of longer duration than the short duration to one of the memory cells, and

a third mode in which the pulse control structure provides no current to one of the memory cells, wherein the plurality of pulse control structures acting simultaneously each provides a current selectable by a plurality of bit line driver circuits, only one of which selects the current at one time.

9. The structure of claim 8, wherein the plurality of bits are in memory cells in a plurality of memory layers of the memory array.

10. The structure of claim 8, wherein the current lower than the high current is less than 60% of the high current.

11. The structure of claim 8, wherein the current lower than the high current is less than 50% of the high current.

12. The structure of claim 8, wherein the longer duration is more than twice the short duration.

13. The structure of claim 8, wherein the longer duration is about five times as long as the short duration.

14. In an integrated circuit comprising an array of memory cells each comprising a phase change material, a structure for simultaneously writing a plurality of bits to the array of memory cells comprising:

a plurality of pulse control structures acting simultaneously, each of the pulse control structures able to operate in three modes,

a first mode in which the pulse control structure provides a high current of short duration to one of the memory cells,

a second mode in which the pulse control structure provides a current lower than the high current and of longer duration than the short duration to one of the memory cells, and

a third mode in which the pulse control structure provides no current to one of the memory cells, wherein the pulse control structures acting simultaneously provide current to a plurality of bit line driver circuits commonly controlled by a bit line decoder output signal.

15. The structure of claim 14, wherein the plurality of bits are in memory cells in a plurality of memory layers of the memory array.

16. The structure of claim 14, wherein the current lower than the high current is less than 60% of the high current.

17. The structure of claim 14, wherein the current lower than the high current is less than 50% of the high current.

18. The structure of claim 14, wherein the longer duration is more than twice the short duration.

19. The structure of claim 14, wherein the longer duration is about five times as long as the short duration.